From 97b4029be73ea5e30b1fe26d3bc2ba43fc0f9d01 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 12 Oct 2020 15:50:35 +0200 Subject: [PATCH] litedram/init: pass write latency calibration capability to software. --- litedram/init.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litedram/init.py b/litedram/init.py index 169a286..6baf31c 100644 --- a/litedram/init.py +++ b/litedram/init.py @@ -508,6 +508,7 @@ def get_sdram_phy_c_header(phy_settings, timing_settings): if phytype in ["USDDRPHY", "USPDDRPHY"]: r += "#define SDRAM_PHY_WRITE_LEVELING_REINIT\n" if phytype in ["USDDRPHY", "USPDDRPHY", "A7DDRPHY", "K7DDRPHY", "V7DDRPHY", "ECP5DDRPHY"]: + r += "#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE\n" r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n" # Define number of modules/delays/bitslips