diff --git a/litedram/core/controller.py b/litedram/core/controller.py index ee0529c..a43c666 100644 --- a/litedram/core/controller.py +++ b/litedram/core/controller.py @@ -30,6 +30,7 @@ class LiteDRAMController(Module): geom_settings.bankbits, phy_settings.dfi_databits, phy_settings.nphases) + self.lasmic = common.Interface( aw=geom_settings.rowbits + geom_settings.colbits - address_align, dw=phy_settings.dfi_databits*phy_settings.nphases, @@ -37,18 +38,32 @@ class LiteDRAMController(Module): req_queue_size=controller_settings.req_queue_size, read_latency=phy_settings.read_latency+1, write_latency=phy_settings.write_latency+1) + self.nrowbits = geom_settings.colbits - address_align # # # - self.submodules.refresher = Refresher(geom_settings.addressbits, geom_settings.bankbits, - timing_settings.tRP, timing_settings.tREFI, timing_settings.tRFC) - self.submodules.bank_machines = [BankMachine(geom_settings, timing_settings, controller_settings, address_align, i, - getattr(self.lasmic, "bank"+str(i))) + self.submodules.refresher = Refresher(geom_settings.addressbits, + geom_settings.bankbits, + timing_settings.tRP, + timing_settings.tREFI,timing_settings.tRFC) + + self.submodules.bank_machines = [BankMachine(geom_settings, + timing_settings, + controller_settings, + address_align, + i, + getattr(self.lasmic, "bank"+str(i))) for i in range(2**geom_settings.bankbits)] - self.submodules.multiplexer = Multiplexer(phy_settings, geom_settings, timing_settings, controller_settings, - self.bank_machines, self.refresher, - self.dfi, self.lasmic) + + self.submodules.multiplexer = Multiplexer(phy_settings, + geom_settings, + timing_settings, + controller_settings, + self.bank_machines, + self.refresher, + self.dfi, + self.lasmic) def get_csrs(self): return self.multiplexer.get_csrs()