From 98f2f24e2025e627731675ea2ecc2feb3737f463 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Boczar?= Date: Fri, 16 Apr 2021 15:12:44 +0200 Subject: [PATCH] init: enable DQ-DQS training for LPDDR4 PHYs with output delays --- litedram/init.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/litedram/init.py b/litedram/init.py index 5d8d53d..4b684c5 100644 --- a/litedram/init.py +++ b/litedram/init.py @@ -690,6 +690,8 @@ def get_sdram_phy_c_header(phy_settings, timing_settings): 'K7LPDDR4PHY', 'V7LPDDR4PHY']: r += "#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE\n" r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n" + if phytype in ['K7LPDDR4PHY', 'V7LPDDR4PHY']: + r += "#define SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE\n" if phytype in ["ECP5DDRPHY"]: r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n" if phytype in ["LPDDR4SIMPHY"]: