From 99f53fcd1f472b4b0734c1d17f49f6f92e8893a2 Mon Sep 17 00:00:00 2001
From: Anton Blanchard <anton@ozlabs.org>
Date: Sun, 3 Oct 2021 19:03:22 +1100
Subject: [PATCH] phy/ecp5ddrphy: set cmd_delay from YAML config

---
 litedram/gen.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/litedram/gen.py b/litedram/gen.py
index 0a7016a..69e6913 100755
--- a/litedram/gen.py
+++ b/litedram/gen.py
@@ -566,7 +566,8 @@ class LiteDRAMCore(SoCCore):
             assert core_config["memtype"] in ["DDR3"]
             self.submodules.ddrphy = sdram_phy = core_config["sdram_phy"](
                 pads         = platform.request("ddram"),
-                sys_clk_freq = sys_clk_freq)
+                sys_clk_freq = sys_clk_freq,
+                cmd_delay    = core_config["cmd_delay"])
             self.ddrphy.settings.add_electrical_settings(
                 rtt_nom = core_config["rtt_nom"],
                 rtt_wr  = core_config["rtt_wr"],