diff --git a/litedram/frontend/wishbone.py b/litedram/frontend/wishbone.py
index 3cb47e5..a83bb8b 100644
--- a/litedram/frontend/wishbone.py
+++ b/litedram/frontend/wishbone.py
@@ -92,7 +92,7 @@ class LiteDRAMWishbone2AXI(Module):
                 port.r.ready.eq(1),
                 wishbone.dat_r.eq(port.r.data),
                 wishbone.ack.eq(1),
-                wishbone.err.eq(port.r.resp != 0b10),
+                wishbone.err.eq(port.r.resp != 0b00),
                 NextState("IDLE")
             )
         )