From 9a50f6ece66a837a0879fba6dd346c7cf68196f8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 6 Nov 2020 14:44:31 +0100 Subject: [PATCH] bench/ddr4_mr_gen.py: change default cl to 9 (cl value for sys_clk_freq=125e6). --- bench/ddr4_mr_gen.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bench/ddr4_mr_gen.py b/bench/ddr4_mr_gen.py index bab6945..0641340 100755 --- a/bench/ddr4_mr_gen.py +++ b/bench/ddr4_mr_gen.py @@ -10,7 +10,7 @@ import argparse parser = argparse.ArgumentParser(description="DDR4 Mode Register settings generator for LiteDRAM.") parser.add_argument("--list", action="store_true", help="List supported DDR4 settings.") -parser.add_argument("--cl", default="11", help="CAS Latency.") +parser.add_argument("--cl", default="9", help="CAS Latency.") parser.add_argument("--cwl", default="9", help="CAS Write Latency.") parser.add_argument("--rtt_nom", default="40ohm", help="RTT_NOM value.") parser.add_argument("--rtt_wr", default="120ohm", help="RTT_WR value.")