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bench/ddr4_mr_gen.py: change default cl to 9 (cl value for sys_clk_freq=125e6).

This commit is contained in:
Florent Kermarrec 2020-11-06 14:44:31 +01:00
parent 4d1f4d5052
commit 9a50f6ece6
1 changed files with 1 additions and 1 deletions
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bench/ddr4_mr_gen.py
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@ -10,7 +10,7 @@ import argparse
parser = argparse.ArgumentParser(description="DDR4 Mode Register settings generator for LiteDRAM.")
parser.add_argument("--list", action="store_true", help="List supported DDR4 settings.")
parser.add_argument("--cl", default="11", help="CAS Latency.")
parser.add_argument("--cl", default="9", help="CAS Latency.")
parser.add_argument("--cwl", default="9", help="CAS Write Latency.")
parser.add_argument("--rtt_nom", default="40ohm", help="RTT_NOM value.")
parser.add_argument("--rtt_wr", default="120ohm", help="RTT_WR value.")