diff --git a/litedram/common.py b/litedram/common.py
index 6a6564e..346b2d3 100644
--- a/litedram/common.py
+++ b/litedram/common.py
@@ -273,14 +273,13 @@ class LiteDRAMNativePort(Settings):
     def __init__(self, mode, address_width, data_width, clock_domain="sys", id=0):
         self.set_attributes(locals())
 
-        self.lock = Signal()
+        self.flush = Signal()
+        self.lock  = Signal()
 
         self.cmd   = stream.Endpoint(cmd_description(address_width))
         self.wdata = stream.Endpoint(wdata_description(data_width))
         self.rdata = stream.Endpoint(rdata_description(data_width))
 
-        self.flush = Signal()
-
         # retro-compatibility # FIXME: remove
         self.aw = self.address_width
         self.dw = self.data_width
@@ -300,6 +299,14 @@ class LiteDRAMNativePort(Settings):
         else:
             return self.cmd.addr[:cba_shift]
 
+    def connect(self, port):
+        return [
+            self.cmd.connect(port.cmd),
+            self.wdata.connect(port.wdata),
+            port.rdata.connect(self.rdata),
+            port.flush.eq(self.flush),
+            self.lock.eq(port.lock),
+        ]
 
 class LiteDRAMNativeWritePort(LiteDRAMNativePort):
     def __init__(self, *args, **kwargs):
diff --git a/litedram/frontend/adapter.py b/litedram/frontend/adapter.py
index 81579a0..da3a7dc 100644
--- a/litedram/frontend/adapter.py
+++ b/litedram/frontend/adapter.py
@@ -358,8 +358,4 @@ class LiteDRAMNativePortConverter(Module):
             self.submodules.converter = LiteDRAMNativePortUpConverter(port_from, port_to, reverse)
         else:
             # Identity
-            self.comb += [
-                port_from.cmd.connect(port_to.cmd),
-                port_from.wdata.connect(port_to.wdata),
-                port_to.rdata.connect(port_from.rdata)
-            ]
+            self.comb += port_from.connect(port_to)