From 9ce84d96ec619059817065a7ccb67be0fd6fb0da Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 29 Oct 2018 19:26:34 +0100
Subject: [PATCH] modules: add MT48LC16M16 (ulx3s)

---
 litedram/modules.py | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/litedram/modules.py b/litedram/modules.py
index 0812e81..1bfc532 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -114,6 +114,17 @@ class MT48LC4M16(SDRAMModule):
     speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=14, tRFC=66, tFAW=None, tRAS=None)}
 
 
+class MT48LC16M16(SDRAMModule):
+    memtype = "SDR"
+    # geometry
+    nbanks = 4
+    nrows  = 8192
+    ncols  = 512
+    # timings
+    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
+    speedgrade_timings = {"default": _SpeedgradeTimings(tRP=18, tRCD=18, tWR=14, tRFC=66, tFAW=None, tRAS=None)}
+
+
 class AS4C16M16(SDRAMModule):
     memtype = "SDR"
     # geometry