diff --git a/litedram/common.py b/litedram/common.py
index a2899bf..4a88511 100644
--- a/litedram/common.py
+++ b/litedram/common.py
@@ -73,12 +73,9 @@ class LiteDRAMInterface(Record):
 
 
 class LiteDRAMPort(Record):
-    def __init__(self, aw, dw, cmd_buffer_depth=0, read_latency=0, write_latency=0):
+    def __init__(self, aw, dw):
         self.aw = aw
         self.dw = dw
-        self.cmd_buffer_depth = cmd_buffer_depth
-        self.read_latency = read_latency
-        self.write_latency = write_latency
 
         layout = cmd_layout(aw) + data_layout(dw)
         Record.__init__(self, layout)
diff --git a/litedram/frontend/crossbar.py b/litedram/frontend/crossbar.py
index db0abff..729c128 100644
--- a/litedram/frontend/crossbar.py
+++ b/litedram/frontend/crossbar.py
@@ -27,10 +27,7 @@ class LiteDRAMCrossbar(Module):
         if self.finalized:
             raise FinalizeError
         port = LiteDRAMPort(self.rca_bits + self.bank_bits,
-                            self.dw,
-                            self.cmd_buffer_depth,
-                            self.read_latency,
-                            self.write_latency)
+                            self.dw)
         self.masters.append(port)
         return port
 
diff --git a/litedram/frontend/dma.py b/litedram/frontend/dma.py
index bf02790..984cd82 100644
--- a/litedram/frontend/dma.py
+++ b/litedram/frontend/dma.py
@@ -5,16 +5,12 @@ from litex.soc.interconnect import stream
 
 
 class LiteDRAMDMAReader(Module):
-    def __init__(self, port, fifo_depth=None):
+    def __init__(self, port, fifo_depth=16):
         self.sink = sink = stream.Endpoint([("address", port.aw)])
         self.source = source = stream.Endpoint([("data", port.dw)])
-        self.busy = Signal()
 
         # # #
 
-        if fifo_depth is None:
-            fifo_depth = port.cmd_buffer_depth + port.read_latency + 2
-
         # request issuance
         request_enable = Signal()
         request_issued = Signal()
@@ -39,10 +35,7 @@ class LiteDRAMDMAReader(Module):
                 rsv_level.eq(rsv_level - 1)
             )
         ]
-        self.comb += [
-            self.busy.eq(rsv_level != 0),
-            request_enable.eq(rsv_level != fifo_depth)
-        ]
+        self.comb += request_enable.eq(rsv_level != fifo_depth)
 
         # FIFO
         fifo = SyncFIFO(port.dw, fifo_depth)
@@ -60,16 +53,12 @@ class LiteDRAMDMAReader(Module):
 
 
 class LiteDRAMDMAWriter(Module):
-    def __init__(self, port, fifo_depth=None):
+    def __init__(self, port, fifo_depth=16):
         self.sink = sink = stream.Endpoint([("address", port.aw),
-                                                ("data", port.dw)])
-        self.busy = Signal()
+                                            ("data", port.dw)])
 
         # # #
 
-        if fifo_depth is None:
-            fifo_depth = port.cmd_buffer_depth + port.write_latency + 2
-
         fifo = SyncFIFO(port.dw, fifo_depth)
         self.submodules += fifo
 
@@ -87,6 +76,5 @@ class LiteDRAMDMAWriter(Module):
                 fifo.re.eq(1),
                 port.wdata_we.eq(2**(port.dw//8)-1),
                 port.wdata.eq(fifo.dout)
-            ),
-            self.busy.eq(fifo.readable)
+            )
         ]