From 9e9c83ce40ae6ea50546b6cc307b9c581ff046ab Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 24 Sep 2021 13:37:19 +0200 Subject: [PATCH] litedram_gen: Add Auto-Flush to UART in FIFO mode. In FIFO mode, backpressure is propagated to the UART and would stall the CPU when the UART is not accepting data. Enable Auto-Flush on the UART to allow DRAM initialization when the UART is not ready. --- litedram/gen.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litedram/gen.py b/litedram/gen.py index 02d2451..d1f131c 100755 --- a/litedram/gen.py +++ b/litedram/gen.py @@ -495,6 +495,7 @@ class LiteDRAMCore(SoCCore): platform.add_extension(get_uart_fifo_ios()) uart_interface = RS232PHYInterface() self.submodules.uart = UART(uart_interface, tx_fifo_depth=1, rx_fifo_depth=1) + self.uart.add_auto_tx_flush(sys_clk_freq=sys_clk_freq, timeout=1, interval=128) uart_tx_pads = platform.request("uart_tx") uart_rx_pads = platform.request("uart_rx") self.comb += [