From 9ef6e4b4443b969df66e91ecae44d6e817b86a20 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Boczar?= Date: Thu, 22 Jul 2021 12:34:34 +0200 Subject: [PATCH] phy/lpddr5/sim: add DFITimingsChecker --- litedram/phy/lpddr5/simsoc.py | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/litedram/phy/lpddr5/simsoc.py b/litedram/phy/lpddr5/simsoc.py index c7b1cf5..37fe432 100644 --- a/litedram/phy/lpddr5/simsoc.py +++ b/litedram/phy/lpddr5/simsoc.py @@ -182,21 +182,21 @@ class SimSoC(SoCCore): self.submodules.ddrctrl = LiteDRAMCoreControl() self.sync += If(self.ddrctrl.init_done.storage, Finish()) - # # Reuse DFITimingsChecker from phy/model.py - # nphases = self.sdram.controller.settings.phy.nphases - # timings = {"tCK": (1e9 / sys_clk_freq) / nphases} - # for name in _speedgrade_timings + _technology_timings: - # timings[name] = sdram_module.get(name) - # - # self.submodules.dfi_timings_checker = DFITimingsChecker( - # dfi = self.ddrphy.dfi, - # nbanks = 2**self.sdram.controller.settings.geom.bankbits, - # nphases = nphases, - # timings = timings, - # refresh_mode = sdram_module.timing_settings.fine_refresh_mode, - # memtype = self.sdram.controller.settings.phy.memtype, - # verbose = False, - # ) + # Reuse DFITimingsChecker from phy/model.py + nphases = self.sdram.controller.settings.phy.nphases + timings = {"tCK": (1e9 / sys_clk_freq) / nphases} + for name in _speedgrade_timings + _technology_timings: + timings[name] = sdram_module.get(name) + + self.submodules.dfi_timings_checker = DFITimingsChecker( + dfi = self.ddrphy.dfi, + nbanks = 2**self.sdram.controller.settings.geom.bankbits, + nphases = nphases, + timings = timings, + refresh_mode = sdram_module.timing_settings.fine_refresh_mode, + memtype = self.sdram.controller.settings.phy.memtype, + verbose = False, + ) # Debug info ------------------------------------------------------------------------------- def dump(obj): @@ -381,4 +381,3 @@ def main(): if __name__ == "__main__": main() -