From 9f9fed02f67d9c4f657742a9a3214b0700f09f6c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 13 Jul 2019 10:31:30 +0200 Subject: [PATCH] test: merge test_downconverter/test_upconverter in a single test_adaptation file --- test/test_adaptation.py | 165 +++++++++++++++++++++++++++++++++++++ test/test_downconverter.py | 93 --------------------- test/test_upconverter.py | 96 --------------------- 3 files changed, 165 insertions(+), 189 deletions(-) create mode 100644 test/test_adaptation.py delete mode 100755 test/test_downconverter.py delete mode 100755 test/test_upconverter.py diff --git a/test/test_adaptation.py b/test/test_adaptation.py new file mode 100644 index 0000000..a5bfe0e --- /dev/null +++ b/test/test_adaptation.py @@ -0,0 +1,165 @@ +# This file is Copyright (c) 2017-2019 Florent Kermarrec +# License: BSD + +import unittest + +from migen import * + +from litex.soc.interconnect.stream import * + +from litedram.common import LiteDRAMNativeWritePort, LiteDRAMNativeReadPort +from litedram.frontend.adaptation import LiteDRAMNativePortConverter + +from test.common import * + +from litex.gen.sim import * + + +class TestAdaptation(unittest.TestCase): + def test_up_converter(self): + class DUT(Module): + def __init__(self): + # write port and converter + self.write_user_port = LiteDRAMNativeWritePort(address_width=32, data_width=32) + self.write_crossbar_port = LiteDRAMNativeWritePort(address_width=32, data_width=128) + write_converter = LiteDRAMNativePortConverter( + self.write_user_port, self.write_crossbar_port) + self.submodules += write_converter + + # read port and converter + self.read_user_port = LiteDRAMNativeReadPort(address_width=32, data_width=32) + self.read_crossbar_port = LiteDRAMNativeReadPort(address_width=32, data_width=128) + read_converter = LiteDRAMNativePortConverter( + self.read_user_port, self.read_crossbar_port) + self.submodules += read_converter + + # memory + self.memory = DRAMMemory(128, 128) + + write_data = [seed_to_data(i, nbits=32) for i in range(16)] + read_data = [] + + @passive + def read_handler(read_port): + yield read_port.rdata.ready.eq(1) + while True: + if (yield read_port.rdata.valid): + read_data.append((yield read_port.rdata.data)) + yield + + + def main_generator(write_port, read_port): + # write + for i in range(16): + yield write_port.cmd.valid.eq(1) + yield write_port.cmd.we.eq(1) + yield write_port.cmd.addr.eq(i) + yield + while (yield write_port.cmd.ready) == 0: + yield + yield write_port.cmd.valid.eq(0) + yield + yield write_port.wdata.valid.eq(1) + yield write_port.wdata.data.eq(write_data[i]) + yield + while (yield write_port.wdata.ready) == 0: + yield + yield write_port.wdata.valid.eq(0) + yield + + # read + for i in range(16): + yield read_port.cmd.valid.eq(1) + yield read_port.cmd.we.eq(0) + yield read_port.cmd.addr.eq(i) + yield + while (yield read_port.cmd.ready) == 0: + yield + yield read_port.cmd.valid.eq(0) + yield + + # delay + for i in range(32): + yield + + dut = DUT() + generators = [ + main_generator(dut.write_user_port, dut.read_user_port), + read_handler(dut.read_user_port), + dut.memory.write_handler(dut.write_crossbar_port), + dut.memory.read_handler(dut.read_crossbar_port) + ] + run_simulation(dut, generators) + self.assertEqual(write_data, read_data) + + def test_down_converter(self): + class DUT(Module): + def __init__(self): + # write port and converter + self.write_user_port = LiteDRAMNativeWritePort(address_width=32, data_width=64) + self.write_crossbar_port = LiteDRAMNativeWritePort(address_width=32, data_width=32) + write_converter = LiteDRAMNativePortConverter( + self.write_user_port, self.write_crossbar_port) + self.submodules += write_converter + + # read port and converter + self.read_user_port = LiteDRAMNativeReadPort(address_width=32, data_width=64) + self.read_crossbar_port = LiteDRAMNativeReadPort(address_width=32, data_width=32) + read_converter = LiteDRAMNativePortConverter( + self.read_user_port, self.read_crossbar_port) + self.submodules += read_converter + + # memory + self.memory = DRAMMemory(32, 128) + + write_data = [seed_to_data(i, nbits=64) for i in range(8)] + read_data = [] + + @passive + def read_handler(read_port): + yield read_port.rdata.ready.eq(1) + while True: + if (yield read_port.rdata.valid): + read_data.append((yield read_port.rdata.data)) + yield + + def main_generator(write_port, read_port): + # write + for i in range(8): + yield write_port.cmd.valid.eq(1) + yield write_port.cmd.we.eq(1) + yield write_port.cmd.addr.eq(i) + yield write_port.wdata.valid.eq(1) + yield write_port.wdata.data.eq(write_data[i]) + yield + while (yield write_port.cmd.ready) == 0: + yield + while (yield write_port.wdata.ready) == 0: + yield + yield + + # read + yield read_port.rdata.ready.eq(1) + for i in range(8): + yield read_port.cmd.valid.eq(1) + yield read_port.cmd.we.eq(0) + yield read_port.cmd.addr.eq(i) + yield + while (yield read_port.cmd.ready) == 0: + yield + yield read_port.cmd.valid.eq(0) + yield + + # latency delay + for i in range(32): + yield + + dut = DUT() + generators = [ + main_generator(dut.write_user_port, dut.read_user_port), + read_handler(dut.read_user_port), + dut.memory.write_handler(dut.write_crossbar_port), + dut.memory.read_handler(dut.read_crossbar_port) + ] + run_simulation(dut, generators) + self.assertEqual(write_data, read_data) diff --git a/test/test_downconverter.py b/test/test_downconverter.py deleted file mode 100755 index 56fc335..0000000 --- a/test/test_downconverter.py +++ /dev/null @@ -1,93 +0,0 @@ -# This file is Copyright (c) 2017-2019 Florent Kermarrec -# License: BSD - -import unittest - -from migen import * - -from litex.soc.interconnect.stream import * - -from litedram.common import LiteDRAMNativeWritePort, LiteDRAMNativeReadPort -from litedram.frontend.adaptation import LiteDRAMNativePortConverter - -from test.common import * - -from litex.gen.sim import * - - -class DUT(Module): - def __init__(self): - # write port and converter - self.write_user_port = LiteDRAMNativeWritePort(address_width=32, data_width=64) - self.write_crossbar_port = LiteDRAMNativeWritePort(address_width=32, data_width=32) - write_converter = LiteDRAMNativePortConverter( - self.write_user_port, self.write_crossbar_port) - self.submodules += write_converter - - # read port and converter - self.read_user_port = LiteDRAMNativeReadPort(address_width=32, data_width=64) - self.read_crossbar_port = LiteDRAMNativeReadPort(address_width=32, data_width=32) - read_converter = LiteDRAMNativePortConverter( - self.read_user_port, self.read_crossbar_port) - self.submodules += read_converter - - # memory - self.memory = DRAMMemory(32, 128) - - -write_data = [seed_to_data(i, nbits=64) for i in range(8)] -read_data = [] - - -@passive -def read_handler(read_port): - yield read_port.rdata.ready.eq(1) - while True: - if (yield read_port.rdata.valid): - read_data.append((yield read_port.rdata.data)) - yield - - -def main_generator(write_port, read_port): - # write - for i in range(8): - yield write_port.cmd.valid.eq(1) - yield write_port.cmd.we.eq(1) - yield write_port.cmd.addr.eq(i) - yield write_port.wdata.valid.eq(1) - yield write_port.wdata.data.eq(write_data[i]) - yield - while (yield write_port.cmd.ready) == 0: - yield - while (yield write_port.wdata.ready) == 0: - yield - yield - - # read - yield read_port.rdata.ready.eq(1) - for i in range(8): - yield read_port.cmd.valid.eq(1) - yield read_port.cmd.we.eq(0) - yield read_port.cmd.addr.eq(i) - yield - while (yield read_port.cmd.ready) == 0: - yield - yield read_port.cmd.valid.eq(0) - yield - - # latency delay - for i in range(32): - yield - - -class TestDownConverter(unittest.TestCase): - def test(self): - dut = DUT() - generators = [ - main_generator(dut.write_user_port, dut.read_user_port), - read_handler(dut.read_user_port), - dut.memory.write_handler(dut.write_crossbar_port), - dut.memory.read_handler(dut.read_crossbar_port) - ] - run_simulation(dut, generators) - self.assertEqual(write_data, read_data) diff --git a/test/test_upconverter.py b/test/test_upconverter.py deleted file mode 100755 index 4afb6a5..0000000 --- a/test/test_upconverter.py +++ /dev/null @@ -1,96 +0,0 @@ -# This file is Copyright (c) 2017-2019 Florent Kermarrec -# License: BSD - -import unittest - -from migen import * - -from litex.soc.interconnect.stream import * - -from litedram.common import LiteDRAMNativeWritePort, LiteDRAMNativeReadPort -from litedram.frontend.adaptation import LiteDRAMNativePortConverter - -from test.common import * - -from litex.gen.sim import * - - -class DUT(Module): - def __init__(self): - # write port and converter - self.write_user_port = LiteDRAMNativeWritePort(address_width=32, data_width=32) - self.write_crossbar_port = LiteDRAMNativeWritePort(address_width=32, data_width=128) - write_converter = LiteDRAMNativePortConverter( - self.write_user_port, self.write_crossbar_port) - self.submodules += write_converter - - # read port and converter - self.read_user_port = LiteDRAMNativeReadPort(address_width=32, data_width=32) - self.read_crossbar_port = LiteDRAMNativeReadPort(address_width=32, data_width=128) - read_converter = LiteDRAMNativePortConverter( - self.read_user_port, self.read_crossbar_port) - self.submodules += read_converter - - # memory - self.memory = DRAMMemory(128, 128) - - -write_data = [seed_to_data(i, nbits=32) for i in range(16)] -read_data = [] - - -@passive -def read_handler(read_port): - yield read_port.rdata.ready.eq(1) - while True: - if (yield read_port.rdata.valid): - read_data.append((yield read_port.rdata.data)) - yield - - -def main_generator(write_port, read_port): - # write - for i in range(16): - yield write_port.cmd.valid.eq(1) - yield write_port.cmd.we.eq(1) - yield write_port.cmd.addr.eq(i) - yield - while (yield write_port.cmd.ready) == 0: - yield - yield write_port.cmd.valid.eq(0) - yield - yield write_port.wdata.valid.eq(1) - yield write_port.wdata.data.eq(write_data[i]) - yield - while (yield write_port.wdata.ready) == 0: - yield - yield write_port.wdata.valid.eq(0) - yield - - # read - for i in range(16): - yield read_port.cmd.valid.eq(1) - yield read_port.cmd.we.eq(0) - yield read_port.cmd.addr.eq(i) - yield - while (yield read_port.cmd.ready) == 0: - yield - yield read_port.cmd.valid.eq(0) - yield - - # delay - for i in range(32): - yield - - -class TestUpConverter(unittest.TestCase): - def test(self): - dut = DUT() - generators = [ - main_generator(dut.write_user_port, dut.read_user_port), - read_handler(dut.read_user_port), - dut.memory.write_handler(dut.write_crossbar_port), - dut.memory.read_handler(dut.read_crossbar_port) - ] - run_simulation(dut, generators) - self.assertEqual(write_data, read_data)