From a11d1b870d23a9647e871afa116777cede3d532d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 2 Jul 2021 09:15:42 +0200 Subject: [PATCH] litedram_gen: Remove device limitation on GENSDRPHY/ECP5DDRPHY. By specifying FPGA device in .yml files for configs requiring it. --- examples/arty.yml | 2 +- examples/genesys2.yml | 2 +- examples/kcu105.yml | 2 +- examples/nexys4ddr.yml | 2 +- examples/ulx3s.yml | 5 +++-- examples/versa_ecp5.yml | 5 +++-- examples/xcu1525.yml | 2 +- litedram/gen.py | 4 ++-- 8 files changed, 13 insertions(+), 11 deletions(-) diff --git a/examples/arty.yml b/examples/arty.yml index 7ec3670..b691a44 100644 --- a/examples/arty.yml +++ b/examples/arty.yml @@ -6,8 +6,8 @@ { # General ------------------------------------------------------------------ - "cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32) "speedgrade": -1, # FPGA speedgrade + "cpu": "vexriscv", # CPU type (ex vexriscv, serv, None) "memtype": "DDR3", # DRAM type # PHY ---------------------------------------------------------------------- diff --git a/examples/genesys2.yml b/examples/genesys2.yml index c1c0108..8295698 100644 --- a/examples/genesys2.yml +++ b/examples/genesys2.yml @@ -6,8 +6,8 @@ { # General ------------------------------------------------------------------ - "cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32) "speedgrade": -2, # FPGA speedgrade + "cpu": "vexriscv", # CPU type (ex vexriscv, serv, None) "memtype": "DDR3", # DRAM type # PHY ---------------------------------------------------------------------- diff --git a/examples/kcu105.yml b/examples/kcu105.yml index 8b7a2d3..96dabe3 100644 --- a/examples/kcu105.yml +++ b/examples/kcu105.yml @@ -6,8 +6,8 @@ { # General ------------------------------------------------------------------ - "cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32) "speedgrade": -2, # FPGA speedgrade + "cpu": "vexriscv", # CPU type (ex vexriscv, serv, None) "memtype": "DDR4", # DRAM type # PHY ---------------------------------------------------------------------- diff --git a/examples/nexys4ddr.yml b/examples/nexys4ddr.yml index 26cc87c..59ecbdf 100644 --- a/examples/nexys4ddr.yml +++ b/examples/nexys4ddr.yml @@ -6,8 +6,8 @@ { # General ------------------------------------------------------------------ - "cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32) "speedgrade": -1, # FPGA speedgrade + "cpu": "vexriscv", # CPU type (ex vexriscv, serv, None) "memtype": "DDR2", # DRAM type # PHY ---------------------------------------------------------------------- diff --git a/examples/ulx3s.yml b/examples/ulx3s.yml index 52002b8..25fe909 100644 --- a/examples/ulx3s.yml +++ b/examples/ulx3s.yml @@ -6,8 +6,9 @@ { # General ------------------------------------------------------------------ - "cpu": "serv", # Type of CPU used for init/calib. - "memtype": "SDR", # DRAM type. + "device": "LFE5U-45F-6BG381C", # FPGA device. + "cpu": "serv", # CPU type (ex vexriscv, serv, None) + "memtype": "SDR", # DRAM type # PHY ---------------------------------------------------------------------- "sdram_module": "MT48LC16M16", # SDRAM modules of the board or SO-DIMM diff --git a/examples/versa_ecp5.yml b/examples/versa_ecp5.yml index a34a602..6392f59 100644 --- a/examples/versa_ecp5.yml +++ b/examples/versa_ecp5.yml @@ -6,8 +6,9 @@ { # General ------------------------------------------------------------------ - "cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32) - "memtype": "DDR3", # DRAM type + "device": "LFE5UM5G-45F-8BG381C", # FPGA device. + "cpu": "vexriscv", # CPU type (ex vexriscv, serv, None) + "memtype": "SDR", # DRAM type # PHY ---------------------------------------------------------------------- "sdram_module": "MT41K64M16", # SDRAM modules of the board or SO-DIMM diff --git a/examples/xcu1525.yml b/examples/xcu1525.yml index 0d9dd02..7822d89 100644 --- a/examples/xcu1525.yml +++ b/examples/xcu1525.yml @@ -6,8 +6,8 @@ { # General ------------------------------------------------------------------ - "cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32) "speedgrade": -2, # FPGA speedgrade + "cpu": "vexriscv", # CPU type (ex vexriscv, serv, None) "memtype": "DDR4", # DRAM type # PHY ---------------------------------------------------------------------- diff --git a/litedram/gen.py b/litedram/gen.py index 1632d3e..59a8ccc 100755 --- a/litedram/gen.py +++ b/litedram/gen.py @@ -746,9 +746,9 @@ def main(): if args.sim: platform = SimPlatform("", io=[]) elif core_config["sdram_phy"] in [litedram_phys.GENSDRPHY]: - platform = LatticePlatform("LFE5U-45F-6BG381C", io=[], toolchain="trellis") # FIXME: Allow other Vendors/Devices. + platform = LatticePlatform(core_config["device"], io=[], toolchain="trellis") # FIXME: Allow other Vendors. elif core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]: - platform = LatticePlatform("LFE5UM5G-45F-8BG381C", io=[], toolchain="trellis") # FIXME: Allow other Vendors/Devices. + platform = LatticePlatform(core_config["device"], io=[], toolchain="trellis") elif core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]: platform = XilinxPlatform("", io=[], toolchain="vivado") elif core_config["sdram_phy"] in [litedram_phys.USDDRPHY, litedram_phys.USPDDRPHY]: