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litedram_gen: Remove device limitation on GENSDRPHY/ECP5DDRPHY. 

By specifying FPGA device in .yml files for configs requiring  it.
This commit is contained in:
Florent Kermarrec 2021-07-02 09:15:42 +02:00
parent 317072a198
commit a11d1b870d
8 changed files with 13 additions and 11 deletions
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2
examples/arty.yml
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@ -6,8 +6,8 @@
{ {
# General ------------------------------------------------------------------ # General ------------------------------------------------------------------
"cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32)
"speedgrade": -1, # FPGA speedgrade "speedgrade": -1, # FPGA speedgrade
"cpu": "vexriscv", # CPU type (ex vexriscv, serv, None)
"memtype": "DDR3", # DRAM type "memtype": "DDR3", # DRAM type
# PHY ---------------------------------------------------------------------- # PHY ----------------------------------------------------------------------

2
examples/genesys2.yml
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@ -6,8 +6,8 @@
{ {
# General ------------------------------------------------------------------ # General ------------------------------------------------------------------
"cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32)
"speedgrade": -2, # FPGA speedgrade "speedgrade": -2, # FPGA speedgrade
"cpu": "vexriscv", # CPU type (ex vexriscv, serv, None)
"memtype": "DDR3", # DRAM type "memtype": "DDR3", # DRAM type
# PHY ---------------------------------------------------------------------- # PHY ----------------------------------------------------------------------

2
examples/kcu105.yml
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@ -6,8 +6,8 @@
{ {
# General ------------------------------------------------------------------ # General ------------------------------------------------------------------
"cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32)
"speedgrade": -2, # FPGA speedgrade "speedgrade": -2, # FPGA speedgrade
"cpu": "vexriscv", # CPU type (ex vexriscv, serv, None)
"memtype": "DDR4", # DRAM type "memtype": "DDR4", # DRAM type
# PHY ---------------------------------------------------------------------- # PHY ----------------------------------------------------------------------

2
examples/nexys4ddr.yml
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@ -6,8 +6,8 @@
{ {
# General ------------------------------------------------------------------ # General ------------------------------------------------------------------
"cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32)
"speedgrade": -1, # FPGA speedgrade "speedgrade": -1, # FPGA speedgrade
"cpu": "vexriscv", # CPU type (ex vexriscv, serv, None)
"memtype": "DDR2", # DRAM type "memtype": "DDR2", # DRAM type
# PHY ---------------------------------------------------------------------- # PHY ----------------------------------------------------------------------

5
examples/ulx3s.yml
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@ -6,8 +6,9 @@
{ {
# General ------------------------------------------------------------------ # General ------------------------------------------------------------------
"cpu": "serv", # Type of CPU used for init/calib. "device": "LFE5U-45F-6BG381C", # FPGA device.
"memtype": "SDR", # DRAM type. "cpu": "serv", # CPU type (ex vexriscv, serv, None)
"memtype": "SDR", # DRAM type
# PHY ---------------------------------------------------------------------- # PHY ----------------------------------------------------------------------
"sdram_module": "MT48LC16M16", # SDRAM modules of the board or SO-DIMM "sdram_module": "MT48LC16M16", # SDRAM modules of the board or SO-DIMM

5
examples/versa_ecp5.yml
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@ -6,8 +6,9 @@
{ {
# General ------------------------------------------------------------------ # General ------------------------------------------------------------------
"cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32) "device": "LFE5UM5G-45F-8BG381C", # FPGA device.
"memtype": "DDR3", # DRAM type "cpu": "vexriscv", # CPU type (ex vexriscv, serv, None)
"memtype": "SDR", # DRAM type
# PHY ---------------------------------------------------------------------- # PHY ----------------------------------------------------------------------
"sdram_module": "MT41K64M16", # SDRAM modules of the board or SO-DIMM "sdram_module": "MT41K64M16", # SDRAM modules of the board or SO-DIMM

2
examples/xcu1525.yml
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@ -6,8 +6,8 @@
{ {
# General ------------------------------------------------------------------ # General ------------------------------------------------------------------
"cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32)
"speedgrade": -2, # FPGA speedgrade "speedgrade": -2, # FPGA speedgrade
"cpu": "vexriscv", # CPU type (ex vexriscv, serv, None)
"memtype": "DDR4", # DRAM type "memtype": "DDR4", # DRAM type
# PHY ---------------------------------------------------------------------- # PHY ----------------------------------------------------------------------

4
litedram/gen.py
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@ -746,9 +746,9 @@ def main():
if args.sim: if args.sim:
platform = SimPlatform("", io=[]) platform = SimPlatform("", io=[])
elif core_config["sdram_phy"] in [litedram_phys.GENSDRPHY]: elif core_config["sdram_phy"] in [litedram_phys.GENSDRPHY]:
platform = LatticePlatform("LFE5U-45F-6BG381C", io=[], toolchain="trellis") # FIXME: Allow other Vendors/Devices. platform = LatticePlatform(core_config["device"], io=[], toolchain="trellis") # FIXME: Allow other Vendors.
elif core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]: elif core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
platform = LatticePlatform("LFE5UM5G-45F-8BG381C", io=[], toolchain="trellis") # FIXME: Allow other Vendors/Devices. platform = LatticePlatform(core_config["device"], io=[], toolchain="trellis")
elif core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]: elif core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]:
platform = XilinxPlatform("", io=[], toolchain="vivado") platform = XilinxPlatform("", io=[], toolchain="vivado")
elif core_config["sdram_phy"] in [litedram_phys.USDDRPHY, litedram_phys.USPDDRPHY]: elif core_config["sdram_phy"] in [litedram_phys.USDDRPHY, litedram_phys.USPDDRPHY]: