From a1e7d805ec8459b212a714a33f6ede55e23a140b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Boczar?= Date: Tue, 19 Jan 2021 13:50:37 +0100 Subject: [PATCH] test: improve error messages when comparing files in test_init.py --- test/test_init.py | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/test/test_init.py b/test/test_init.py index 9d1ee84..0f251ce 100644 --- a/test/test_init.py +++ b/test/test_init.py @@ -5,19 +5,20 @@ # SPDX-License-Identifier: BSD-2-Clause import os -import filecmp +import difflib import unittest -from litex.build.tools import write_to_file - from litedram.init import get_sdram_phy_c_header, get_sdram_phy_py_header -def compare_with_reference(content, filename): - write_to_file(filename, content) - r = filecmp.cmp(filename, os.path.join("test", "reference", filename)) - os.remove(filename) - return r +def compare_with_reference(test_case, content, filename): + ref_filename = os.path.join("test", "reference", filename) + with open(ref_filename, "r") as f: + reference = f.read().split("\n") + content = content.split("\n") + diff = list(difflib.unified_diff(content, reference, fromfile=filename, tofile=ref_filename)) + msg = "Unified diff:\n" + "\n".join(diff) + test_case.assertEqual(len(diff), 0, msg=msg) class TestInit(unittest.TestCase): @@ -26,21 +27,21 @@ class TestInit(unittest.TestCase): soc = BaseSoC() c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) - self.assertEqual(compare_with_reference(c_header, "sdr_init.h"), True) - self.assertEqual(compare_with_reference(py_header, "sdr_init.py"), True) + compare_with_reference(self, c_header, "sdr_init.h") + compare_with_reference(self, py_header, "sdr_init.py") def test_ddr3(self): from litex_boards.targets.kc705 import BaseSoC soc = BaseSoC() c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) - self.assertEqual(compare_with_reference(c_header, "ddr3_init.h"), True) - self.assertEqual(compare_with_reference(py_header, "ddr3_init.py"), True) + compare_with_reference(self, c_header, "ddr3_init.h") + compare_with_reference(self, py_header, "ddr3_init.py") def test_ddr4(self): from litex_boards.targets.kcu105 import BaseSoC soc = BaseSoC(max_sdram_size=0x4000000) c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) - self.assertEqual(compare_with_reference(c_header, "ddr4_init.h"), True) - self.assertEqual(compare_with_reference(py_header, "ddr4_init.py"), True) + compare_with_reference(self, c_header, "ddr4_init.h") + compare_with_reference(self, py_header, "ddr4_init.py")