From a21b70e06150fdbeaf609dba039009f5e30e3df9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Boczar?= Date: Tue, 23 Mar 2021 11:17:54 +0100 Subject: [PATCH] init: revert bitslips changed to 16 for phys other than S7LPDDR4PHY --- litedram/init.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/litedram/init.py b/litedram/init.py index 4b7e8d5..c0985d6 100644 --- a/litedram/init.py +++ b/litedram/init.py @@ -698,7 +698,11 @@ def get_sdram_phy_c_header(phy_settings, timing_settings): r += "#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2\n" r += "#define SDRAM_PHY_DELAYS 512\n" r += "#define SDRAM_PHY_BITSLIPS 8\n" - elif phytype in ["A7DDRPHY", "K7DDRPHY", "V7DDRPHY", "S7LPDDR4PHY"]: + elif phytype in ["A7DDRPHY", "K7DDRPHY", "V7DDRPHY"]: + r += "#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2\n" + r += "#define SDRAM_PHY_DELAYS 32\n" + r += "#define SDRAM_PHY_BITSLIPS 8\n" + elif phytype in ["S7LPDDR4PHY"]: r += "#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2\n" r += "#define SDRAM_PHY_DELAYS 32\n" r += "#define SDRAM_PHY_BITSLIPS 16\n"