diff --git a/litedram/phy/lpddr4/simsoc.py b/litedram/phy/lpddr4/simsoc.py
index 1b9a86c..b284dd0 100644
--- a/litedram/phy/lpddr4/simsoc.py
+++ b/litedram/phy/lpddr4/simsoc.py
@@ -123,7 +123,7 @@ class SimSoC(SoCCore):
             clk_freq      = sys_clk_freq,
             ident         = "LiteX Simulation",
             ident_version = True,
-            cpu_variant   = "minimal",
+            cpu_variant   = "lite",
             **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
diff --git a/test/test_lpddr4.py b/test/test_lpddr4.py
index 81f8a9a..806f8c9 100644
--- a/test/test_lpddr4.py
+++ b/test/test_lpddr4.py
@@ -692,15 +692,15 @@ class VerilatorLPDDR4Tests(unittest.TestCase):
 
         self.check_logs(p.before.decode())
 
-    #def test_lpddr4_sim_x2rate_no_cache(self):
-    #    # Test simulation with regular delays, intermediate serialization stage,
-    #    # refresh and no L2 cache (masked write must work)
-    #    self.run_test([
-    #        "--finish-after-memtest", "--log-level", "warn",
-    #        "--double-rate-phy",
-    #        "--l2-size", "0",
-    #        "--no-refresh",  # FIXME: LiteDRAM sends refresh commands when only MRW/MRR are allowed
-    #    ])
+    def test_lpddr4_sim_x2rate_no_cache(self):
+        # Test simulation with regular delays, intermediate serialization stage,
+        # refresh and no L2 cache (masked write must work)
+        self.run_test([
+            "--finish-after-memtest", "--log-level", "warn",
+            "--double-rate-phy",
+            "--l2-size", "0",
+            "--no-refresh",  # FIXME: LiteDRAM sends refresh commands when only MRW/MRR are allowed
+        ])
 
     def test_lpddr4_sim_fast(self):
         # Fast test of simulation with L2 cache (so no data masking is required)