diff --git a/litedram/common.py b/litedram/common.py index 7507a61..4d0fc68 100644 --- a/litedram/common.py +++ b/litedram/common.py @@ -178,7 +178,6 @@ class PhySettings(Settings): def __init__(self, phytype, memtype, databits, dfi_databits, nphases, rdphase, wrphase, - rdcmdphase, wrcmdphase, cl, read_latency, write_latency, nranks=1, cwl=None, cmd_latency=None, cmd_delay=None): self.set_attributes(locals()) diff --git a/litedram/core/multiplexer.py b/litedram/core/multiplexer.py index d7e1d04..a0e9df6 100644 --- a/litedram/core/multiplexer.py +++ b/litedram/core/multiplexer.py @@ -226,6 +226,21 @@ class Multiplexer(Module, AutoCSR): ras_allowed = Signal(reset=1) cas_allowed = Signal(reset=1) + # Read/Write Cmd/Dat phases ---------------------------------------------------------------- + nphases = settings.phy.nphases + rdphase = settings.phy.rdphase + wrphase = settings.phy.wrphase + if isinstance(rdphase, Signal): + rdcmdphase = Signal.like(rdphase) + self.comb += rdcmdphase.eq(rdphase - 1) # Implicit %nphases. + else: + rdcmdphase = (rdphase - 1)%nphases + if isinstance(rdphase, Signal): + wrcmdphase = Signal.like(wrphase) + self.comb += wrcmdphase.eq(wrphase - 1) # Implicit %nphases. + else: + wrcmdphase = (wrphase - 1)%nphases + # Command choosing ------------------------------------------------------------------------- requests = [bm.cmd for bm in bank_machines] self.submodules.choose_cmd = choose_cmd = _CommandChooser(requests) @@ -320,14 +335,14 @@ class Multiplexer(Module, AutoCSR): def steerer_sel(steerer, access): assert access in ["read", "write"] r = [] - for i in range(settings.phy.nphases): + for i in range(nphases): r.append(steerer.sel[i].eq(STEER_NOP)) if access == "read": - r.append(If(i == settings.phy.rdphase, steerer.sel[i].eq(STEER_REQ))) - r.append(If(i == settings.phy.rdcmdphase, steerer.sel[i].eq(STEER_CMD))) + r.append(If(i == rdphase, steerer.sel[i].eq(STEER_REQ))) + r.append(If(i == rdcmdphase, steerer.sel[i].eq(STEER_CMD))) if access == "write": - r.append(If(i == settings.phy.wrphase, steerer.sel[i].eq(STEER_REQ))) - r.append(If(i == settings.phy.wrcmdphase, steerer.sel[i].eq(STEER_CMD))) + r.append(If(i == wrphase, steerer.sel[i].eq(STEER_REQ))) + r.append(If(i == wrcmdphase, steerer.sel[i].eq(STEER_CMD))) return r # Control FSM ------------------------------------------------------------------------------ diff --git a/litedram/phy/ecp5ddrphy.py b/litedram/phy/ecp5ddrphy.py index e6ecbde..ec5aa6d 100644 --- a/litedram/phy/ecp5ddrphy.py +++ b/litedram/phy/ecp5ddrphy.py @@ -133,8 +133,6 @@ class ECP5DDRPHY(Module, AutoCSR): nphases = nphases, rdphase = rdphase, wrphase = wrphase, - rdcmdphase = (rdphase - 1)%nphases, - wrcmdphase = (wrphase - 1)%nphases, cl = cl, cwl = cwl, read_latency = cl_sys_latency + 10, diff --git a/litedram/phy/gensdrphy.py b/litedram/phy/gensdrphy.py index ad77b87..f15dbdf 100644 --- a/litedram/phy/gensdrphy.py +++ b/litedram/phy/gensdrphy.py @@ -36,8 +36,6 @@ class GENSDRPHY(Module): nphases = 1, rdphase = 0, wrphase = 0, - rdcmdphase = 0, - wrcmdphase = 0, cl = cl, read_latency = cl + cmd_latency, write_latency = 0 @@ -121,8 +119,6 @@ class HalfRateGENSDRPHY(Module): nphases = nphases, rdphase = 0, wrphase = 0, - rdcmdphase = 1, - wrcmdphase = 1, cl = cl, read_latency = (cl + cmd_latency)//2 + 1, write_latency = 0 diff --git a/litedram/phy/s6ddrphy.py b/litedram/phy/s6ddrphy.py index 011fdd6..ab96bcd 100644 --- a/litedram/phy/s6ddrphy.py +++ b/litedram/phy/s6ddrphy.py @@ -57,8 +57,6 @@ class S6HalfRateDDRPHY(Module): nphases = nphases, rdphase = 0, wrphase = 1, - rdcmdphase = 1, - wrcmdphase = 0, cl = 5, cwl = 6, read_latency = 6, @@ -74,8 +72,6 @@ class S6HalfRateDDRPHY(Module): nphases = nphases, rdphase = 0, wrphase = 1, - rdcmdphase = 1, - wrcmdphase = 0, cl = 3, read_latency = 5, write_latency = 0 diff --git a/litedram/phy/s7ddrphy.py b/litedram/phy/s7ddrphy.py index 4bc4644..002410e 100644 --- a/litedram/phy/s7ddrphy.py +++ b/litedram/phy/s7ddrphy.py @@ -86,13 +86,6 @@ class S7DDRPHY(Module, AutoCSR): self._wrphase = CSRStorage(2, reset=wrphase) # PHY settings ----------------------------------------------------------------------------- - _rdphase = self._rdphase.storage - _wrphase = self._wrphase.storage - _rdcmdphase = Signal(2) - _wrcmdphase = Signal(2) - self.comb += _rdcmdphase.eq(_rdphase - 1) - self.comb += _wrcmdphase.eq(_wrphase - 1) - self.settings = PhySettings( phytype = phytype, memtype = memtype, @@ -100,10 +93,8 @@ class S7DDRPHY(Module, AutoCSR): dfi_databits = 2*databits, nranks = nranks, nphases = nphases, - rdphase = _rdphase, - wrphase = _wrphase, - rdcmdphase = _rdcmdphase, - wrcmdphase = _wrcmdphase, + rdphase = self._rdphase.storage, + wrphase = self._wrphase.storage, cl = cl, cwl = cwl, read_latency = cl_sys_latency + 6, diff --git a/litedram/phy/usddrphy.py b/litedram/phy/usddrphy.py index 0ad3ef7..0e08087 100644 --- a/litedram/phy/usddrphy.py +++ b/litedram/phy/usddrphy.py @@ -85,13 +85,6 @@ class USDDRPHY(Module, AutoCSR): self._wrphase = CSRStorage(2, reset=wrphase) # PHY settings ----------------------------------------------------------------------------- - _rdphase = self._rdphase.storage - _wrphase = self._wrphase.storage - _rdcmdphase = Signal(2) - _wrcmdphase = Signal(2) - self.comb += _rdcmdphase.eq(_rdphase - 1) - self.comb += _wrcmdphase.eq(_wrphase - 1) - self.settings = PhySettings( phytype = phytype, memtype = memtype, @@ -99,10 +92,8 @@ class USDDRPHY(Module, AutoCSR): dfi_databits = 2*databits, nranks = nranks, nphases = nphases, - rdphase = _rdphase, - wrphase = _wrphase, - rdcmdphase = _rdcmdphase, - wrcmdphase = _wrcmdphase, + rdphase = self._rdphase.storage, + wrphase = self._wrphase.storage, cl = cl, cwl = cwl, read_latency = cl_sys_latency + 5,