From a611778e3d4bb6d881f7c656cea23e8449bc33cb Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 30 Sep 2020 19:19:31 +0200 Subject: [PATCH] litedram/init/get_sdram_phy_c_header: add CL/CWL defines. --- litedram/init.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/litedram/init.py b/litedram/init.py index fc24678..169a286 100644 --- a/litedram/init.py +++ b/litedram/init.py @@ -485,6 +485,10 @@ def get_sdram_phy_c_header(phy_settings, timing_settings): r += "#define SDRAM_PHY_XDR "+str(1 if phy_settings.memtype == "SDR" else 2) + "\n" r += "#define SDRAM_PHY_DATABITS "+str(phy_settings.databits) + "\n" r += "#define SDRAM_PHY_PHASES "+str(nphases)+"\n" + if phy_settings.cl is not None: + r += "#define SDRAM_PHY_CL "+str(phy_settings.cl)+"\n" + if phy_settings.cwl is not None: + r += "#define SDRAM_PHY_CWL "+str(phy_settings.cwl)+"\n" if phy_settings.cmd_latency is not None: r += "#define SDRAM_PHY_CMD_LATENCY "+str(phy_settings.cmd_latency)+"\n" if phy_settings.cmd_delay is not None: