From a72ba87f3e8c24c8ccf8a851a316b2450e8b1220 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 7 Jul 2017 15:56:23 +0200 Subject: [PATCH] phy/kusddrphy: use fixed delays for initial board test, identify strange behaviour of IOBUF... --- litedram/phy/kusddrphy.py | 65 +++++++++++++++++++-------------------- 1 file changed, 32 insertions(+), 33 deletions(-) diff --git a/litedram/phy/kusddrphy.py b/litedram/phy/kusddrphy.py index a882d6f..d33e6b5 100644 --- a/litedram/phy/kusddrphy.py +++ b/litedram/phy/kusddrphy.py @@ -10,8 +10,8 @@ from litedram.common import PhySettings from litedram.phy.dfi import * # TODO: -# - verify initial p_DELAY_VALUE on ODELAYE3/IDELAYE3 -# - test on board +# - fix IOBUF behaviour +# - revert IDELAYE3/ODELAYE3 taps control class KUSDDRPHY(Module, AutoCSR): def __init__(self, pads): @@ -20,8 +20,6 @@ class KUSDDRPHY(Module, AutoCSR): databits = len(pads.dq) nphases = 4 - self._rst = CSRStorage() - self._wlevel_en = CSRStorage() self._wlevel_strobe = CSR() @@ -54,8 +52,6 @@ class KUSDDRPHY(Module, AutoCSR): # # # - rst = self._rst.storage - # Clock sd_clk_se = Signal() self.specials += [ @@ -64,7 +60,7 @@ class KUSDDRPHY(Module, AutoCSR): p_IS_CLK_INVERTED=0, p_IS_CLKDIV_INVERTED=0, p_IS_RST_INVERTED=0, o_OQ=sd_clk_se, - i_RST=ResetSignal() | rst, + i_RST=ResetSignal(), i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(), i_D=0b10101010 ), @@ -83,7 +79,7 @@ class KUSDDRPHY(Module, AutoCSR): p_IS_CLK_INVERTED=0, p_IS_CLKDIV_INVERTED=0, p_IS_RST_INVERTED=0, o_OQ=pads.a[i], - i_RST=ResetSignal() | rst, + i_RST=ResetSignal(), i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(), i_D=Cat(self.dfi.phases[0].address[i], self.dfi.phases[0].address[i], self.dfi.phases[1].address[i], self.dfi.phases[1].address[i], @@ -97,7 +93,7 @@ class KUSDDRPHY(Module, AutoCSR): p_IS_CLK_INVERTED=0, p_IS_CLKDIV_INVERTED=0, p_IS_RST_INVERTED=0, o_OQ=pads.ba[i], - i_RST=ResetSignal() | rst, + i_RST=ResetSignal(), i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(), i_D=Cat(self.dfi.phases[0].bank[i], self.dfi.phases[0].bank[i], self.dfi.phases[1].bank[i], self.dfi.phases[1].bank[i], @@ -111,7 +107,7 @@ class KUSDDRPHY(Module, AutoCSR): p_IS_CLK_INVERTED=0, p_IS_CLKDIV_INVERTED=0, p_IS_RST_INVERTED=0, o_OQ=getattr(pads, name), - i_RST=ResetSignal() | rst, + i_RST=ResetSignal(), i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(), i_D=Cat(getattr(self.dfi.phases[0], name), getattr(self.dfi.phases[0], name), getattr(self.dfi.phases[1], name), getattr(self.dfi.phases[1], name), @@ -140,7 +136,7 @@ class KUSDDRPHY(Module, AutoCSR): p_IS_CLK_INVERTED=0, p_IS_CLKDIV_INVERTED=0, p_IS_RST_INVERTED=0, o_OQ=dm_o_nodelay, - i_RST=ResetSignal() | rst, + i_RST=ResetSignal(), i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(), i_D=Cat(self.dfi.phases[0].wrdata_mask[i], self.dfi.phases[0].wrdata_mask[databits//8+i], self.dfi.phases[1].wrdata_mask[i], self.dfi.phases[1].wrdata_mask[databits//8+i], @@ -151,12 +147,12 @@ class KUSDDRPHY(Module, AutoCSR): Instance("ODELAYE3", p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=200.0, p_IS_CLK_INVERTED=0, p_IS_RST_INVERTED=0, - p_DELAY_FORMAT="COUNT", p_DELAY_TYPE="VARIABLE", p_DELAY_VALUE=0, + p_DELAY_FORMAT="TIME", p_DELAY_TYPE="FIXED", p_DELAY_VALUE=0, i_CLK=ClockSignal(), - i_INC=1, i_EN_VTC=0, - i_RST=(self._dly_sel.storage[i] & self._wdly_dq_rst.re) | rst, - i_CE=self._dly_sel.storage[i] & self._wdly_dq_inc.re, + i_INC=0, i_EN_VTC=1, + i_RST=0, + i_CE=0, o_ODATAIN=dm_o_nodelay, o_DATAOUT=pads.dm[i] ) @@ -170,7 +166,7 @@ class KUSDDRPHY(Module, AutoCSR): p_IS_CLK_INVERTED=0, p_IS_CLKDIV_INVERTED=0, p_IS_RST_INVERTED=0, o_OQ=dqs_nodelay, o_T_OUT=dqs_t, - i_RST=ResetSignal() | rst, + i_RST=ResetSignal(), i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(), i_D=Cat(dqs_serdes_pattern[0], dqs_serdes_pattern[1], dqs_serdes_pattern[2], dqs_serdes_pattern[3], @@ -181,12 +177,12 @@ class KUSDDRPHY(Module, AutoCSR): Instance("ODELAYE3", p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=200.0, p_IS_CLK_INVERTED=0, p_IS_RST_INVERTED=0, - p_DELAY_FORMAT="COUNT", p_DELAY_TYPE="VARIABLE", p_DELAY_VALUE=6, # TODO: verify value + p_DELAY_FORMAT="TIME", p_DELAY_TYPE="FIXED", p_DELAY_VALUE=500, i_CLK=ClockSignal(), - i_INC=1, i_EN_VTC=0, - i_RST=(self._dly_sel.storage[i] & self._wdly_dqs_rst.re) | rst, - i_CE=self._dly_sel.storage[i] & self._wdly_dqs_inc.re, + i_INC=0, i_EN_VTC=1, + i_RST=0, + i_CE=0, o_ODATAIN=dqs_nodelay, o_DATAOUT=dqs_delayed ), @@ -228,7 +224,7 @@ class KUSDDRPHY(Module, AutoCSR): p_DATA_WIDTH=8, i_D=dq_i_delayed, - i_RST=ResetSignal() | rst, + i_RST=ResetSignal(), i_FIFO_RD_CLK=0, i_FIFO_RD_EN=0, i_CLK=ClockSignal("sys4x"), i_CLK_B=~ClockSignal("sys4x"), i_CLKDIV=ClockSignal(), o_Q=dq_bitslip.i @@ -236,30 +232,33 @@ class KUSDDRPHY(Module, AutoCSR): Instance("ODELAYE3", p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=200.0, p_IS_CLK_INVERTED=0, p_IS_RST_INVERTED=0, - p_DELAY_FORMAT="COUNT", p_DELAY_TYPE="VARIABLE", p_DELAY_VALUE=6, # TODO: verify value - + p_DELAY_FORMAT="TIME", p_DELAY_TYPE="FIXED", p_DELAY_VALUE=0, + i_CLK=ClockSignal(), - i_INC=1, i_EN_VTC=0, - i_RST=(self._dly_sel.storage[i//8] & self._wdly_dq_rst.re) | rst, - i_CE=self._dly_sel.storage[i//8] & self._wdly_dq_inc.re, - + i_INC=0, i_EN_VTC=1, + i_RST=0, + i_CE=0, + o_ODATAIN=dq_o_nodelay, o_DATAOUT=dq_o_delayed ), Instance("IDELAYE3", p_CASCADE="NONE", p_UPDATE_MODE="ASYNC",p_REFCLK_FREQUENCY=200.0, p_IS_CLK_INVERTED=0, p_IS_RST_INVERTED=0, - p_DELAY_FORMAT="COUNT", p_DELAY_SRC="IDATAIN", - p_DELAY_TYPE="VARIABLE", p_DELAY_VALUE=6, # TODO: verify value + p_DELAY_FORMAT="TIME", p_DELAY_SRC="IDATAIN", + p_DELAY_TYPE="FIXED", p_DELAY_VALUE=0, i_CLK=ClockSignal(), - i_INC=1, i_EN_VTC=0, - i_RST=(self._dly_sel.storage[i//8] & self._rdly_dq_rst.re) | rst, - i_CE=self._dly_sel.storage[i//8] & self._rdly_dq_inc.re, + i_INC=0, i_EN_VTC=1, + i_RST=0, + i_CE=0, i_IDATAIN=dq_i_nodelay, o_DATAOUT=dq_i_delayed ), Instance("IOBUF", - i_I=dq_o_delayed, o_O=dq_i_nodelay, i_T=dq_t, + #i_I=0, o_O=dq_i_nodelay, i_T=dq_t, # input working... + #i_I=1, o_O=dq_i_nodelay, i_T=dq_t, # input working... + i_I=dq_o_delayed, o_O=dq_i_nodelay, i_T=dq_t, # input not working... : why ?? + io_IO=pads.dq[i] ) ]