From 3b0ec8f9969f81e8494b0f33e1ef655eed9ac1f1 Mon Sep 17 00:00:00 2001
From: Piotr Binkowski <pbinkowski@antmicro.com>
Date: Wed, 26 Feb 2020 12:31:34 +0100
Subject: [PATCH] modules: add KVR21SE15S8/4 SO-DIMM

---
 litedram/modules.py | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/litedram/modules.py b/litedram/modules.py
index ddd2073..0473bd5 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -557,3 +557,21 @@ class MT40A512M16(SDRAMModule):
         "2400": _SpeedgradeTimings(tRP=13.32, tRCD=13.32, tWR=15, tRFC=trfc, tFAW=(20, 25), tRAS=32),
     }
     speedgrade_timings["default"] = speedgrade_timings["2400"]
+
+# DDR4 (SO-DIMM) -----------------------------------------------------------------------------------
+class KVR21SE15S84(SDRAMModule):
+    memtype = "DDR4"
+    # geometry
+    ngroupbanks = 4
+    ngroups     = 4
+    nbanks      = ngroups * ngroupbanks
+    nrows       = 32768
+    ncols       = 1024
+    # timings
+    trefi = {"1x": 64e6/8192,   "2x": (64e6/8192)/2, "4x": (64e6/8192)/4}
+    trfc  = {"1x": (None, 350), "2x": (None, 260),   "4x": (None, 160)}
+    technology_timings = _TechnologyTimings(tREFI=trefi, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 4.9), tZQCS=(128, 80))
+    speedgrade_timings = {
+        "2133": _SpeedgradeTimings(tRP=13.5, tRCD=13.5, tWR=15, tRFC=trfc, tFAW=(20, 25), tRAS=33),
+    }
+    speedgrade_timings["default"] = speedgrade_timings["2133"]