diff --git a/litedram/phy/s7ddrphy_halfrate_bl8.py b/litedram/phy/s7ddrphy_halfrate_bl8.py
index a48f06c..f057cae 100644
--- a/litedram/phy/s7ddrphy_halfrate_bl8.py
+++ b/litedram/phy/s7ddrphy_halfrate_bl8.py
@@ -444,10 +444,10 @@ class S7DDRPHY(Module, AutoCSR):
         elif memtype == "DDR3":
             dqs_sys_latency = cwl_sys_latency-1 if with_odelay else cwl_sys_latency
         self.comb += [
-            dqs_preamble.eq(last_wrdata_en[dqs_sys_latency-1] &
-                            ~last_wrdata_en[dqs_sys_latency]),
-            dqs_postamble.eq(last_wrdata_en[dqs_sys_latency+2] &
-                            ~last_wrdata_en[dqs_sys_latency+1]),
+            #dqs_preamble.eq(last_wrdata_en[dqs_sys_latency-1] &
+            #                ~last_wrdata_en[dqs_sys_latency]),
+            #dqs_postamble.eq(last_wrdata_en[dqs_sys_latency+2] &
+            #                ~last_wrdata_en[dqs_sys_latency+1]),
         ]