From a8d26724ddf8f75ee29a9a2986080dba037b05b0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 15 Sep 2018 01:50:53 +0200 Subject: [PATCH] phy/s7ddrphy_halfrate_bl8: don't generate dqs pre/post-amble, needs simulation --- litedram/phy/s7ddrphy_halfrate_bl8.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/litedram/phy/s7ddrphy_halfrate_bl8.py b/litedram/phy/s7ddrphy_halfrate_bl8.py index a48f06c..f057cae 100644 --- a/litedram/phy/s7ddrphy_halfrate_bl8.py +++ b/litedram/phy/s7ddrphy_halfrate_bl8.py @@ -444,10 +444,10 @@ class S7DDRPHY(Module, AutoCSR): elif memtype == "DDR3": dqs_sys_latency = cwl_sys_latency-1 if with_odelay else cwl_sys_latency self.comb += [ - dqs_preamble.eq(last_wrdata_en[dqs_sys_latency-1] & - ~last_wrdata_en[dqs_sys_latency]), - dqs_postamble.eq(last_wrdata_en[dqs_sys_latency+2] & - ~last_wrdata_en[dqs_sys_latency+1]), + #dqs_preamble.eq(last_wrdata_en[dqs_sys_latency-1] & + # ~last_wrdata_en[dqs_sys_latency]), + #dqs_postamble.eq(last_wrdata_en[dqs_sys_latency+2] & + # ~last_wrdata_en[dqs_sys_latency+1]), ]