diff --git a/litedram/common.py b/litedram/common.py
index 0120a0a..9ace716 100644
--- a/litedram/common.py
+++ b/litedram/common.py
@@ -71,6 +71,7 @@ def data_layout(data_width):
 class LiteDRAMInterface(Record):
     def __init__(self, address_align, settings):
         rankbits = log2_int(settings.phy.nranks)
+        self.address_align = address_align
         self.address_width = settings.geom.rowbits + settings.geom.colbits + rankbits - address_align
         self.data_width = settings.phy.dfi_databits*settings.phy.nphases
         self.nbanks = settings.phy.nranks*(2**settings.geom.bankbits)
diff --git a/litedram/core/controller.py b/litedram/core/controller.py
index f196657..a0c9d3b 100644
--- a/litedram/core/controller.py
+++ b/litedram/core/controller.py
@@ -22,6 +22,7 @@ class ControllerSettings(Settings):
 class LiteDRAMController(Module):
     def __init__(self, phy_settings, geom_settings, timing_settings,
                  controller_settings=ControllerSettings()):
+        address_align = log2_int(burst_lengths[phy_settings.memtype])
         self.settings = settings = controller_settings
         self.settings.phy = phy_settings
         self.settings.geom = geom_settings
@@ -34,13 +35,10 @@ class LiteDRAMController(Module):
             phy_settings.dfi_databits,
             phy_settings.nphases)
 
-        address_align = log2_int(burst_lengths[phy_settings.memtype])
         self.interface = interface = LiteDRAMInterface(address_align, settings)
 
         # # #
 
-        self.nrowbits = settings.geom.colbits - address_align # FIXME
-
         # refresher
         refresher = Refresher(settings)
         self.submodules += refresher
diff --git a/litedram/core/crossbar.py b/litedram/core/crossbar.py
index ec2243d..8d22330 100644
--- a/litedram/core/crossbar.py
+++ b/litedram/core/crossbar.py
@@ -12,10 +12,14 @@ from litedram.common import *
 from litedram.frontend.adaptation import *
 
 
+ROW_BANK_COL = 0b01
+ROW_COL_BANK = 0b10
+
+
 class LiteDRAMCrossbar(Module):
-    def __init__(self, controller, cba_shift):
+    def __init__(self, controller, address_mapping=ROW_BANK_COL):
         self.controller = controller
-        self.cba_shift = cba_shift
+        self.address_mapping = address_mapping
 
         self.rca_bits = controller.address_width
         self.nbanks = controller.nbanks
@@ -86,8 +90,17 @@ class LiteDRAMCrossbar(Module):
     def do_finalize(self):
         nmasters = len(self.masters)
 
-        m_ba = [m.get_bank_address(self.bank_bits, self.cba_shift)for m in self.masters]
-        m_rca = [m.get_row_column_address(self.bank_bits, self.rca_bits, self.cba_shift) for m in self.masters]
+        # address mapping
+        cba_shift = {
+            ROW_BANK_COL: self.controller.settings.geom.colbits -
+                          self.controller.address_align,
+            ROW_COL_BANK: self.controller.settings.geom.rowbits +
+                          self.controller.settings.geom.colbits -
+                          self.controller.address_align
+        }
+
+        m_ba = [m.get_bank_address(self.bank_bits, cba_shift[self.address_mapping])for m in self.masters]
+        m_rca = [m.get_row_column_address(self.bank_bits, self.rca_bits, cba_shift[self.address_mapping]) for m in self.masters]
 
         controller = self.controller
         master_readys = [0]*nmasters