diff --git a/litedram/common.py b/litedram/common.py
index 769071e..76b3121 100644
--- a/litedram/common.py
+++ b/litedram/common.py
@@ -44,8 +44,8 @@ def cmd_layout(aw):
     return [
         ("valid",        1, DIR_M_TO_S),
         ("ready",        1, DIR_S_TO_M),
-        ("we",           1, DIR_M_TO_S),
-        ("adr",         aw, DIR_M_TO_S),
+        ("we",           1, DIR_M_TO_S, True),
+        ("adr",         aw, DIR_M_TO_S, True),
         ("lock",         1, DIR_S_TO_M), # only used internally
 
         ("wdata_ready",  1, DIR_S_TO_M),
@@ -55,9 +55,9 @@ def cmd_layout(aw):
 
 def data_layout(dw):
     return [
-        ("wdata",       dw, DIR_M_TO_S),
-        ("wdata_we", dw//8, DIR_M_TO_S),
-        ("rdata",       dw, DIR_S_TO_M)
+        ("wdata",       dw, DIR_M_TO_S, True),
+        ("wdata_we", dw//8, DIR_M_TO_S, True),
+        ("rdata",       dw, DIR_S_TO_M, True)
     ]
 
 
diff --git a/litedram/core/bankmachine.py b/litedram/core/bankmachine.py
index d099b38..7a0cd73 100644
--- a/litedram/core/bankmachine.py
+++ b/litedram/core/bankmachine.py
@@ -57,7 +57,7 @@ class BankMachine(Module):
 
         # Row tracking
         has_openrow = Signal()
-        openrow = Signal(settings.geom.rowbits)
+        openrow = Signal(settings.geom.rowbits, reset_less=True)
         hit = Signal()
         self.comb += hit.eq(openrow == slicer.row(cmd_buffer.source.adr))
         track_open = Signal()
diff --git a/litedram/phy/dfi.py b/litedram/phy/dfi.py
index 2581212..cfb62cb 100644
--- a/litedram/phy/dfi.py
+++ b/litedram/phy/dfi.py
@@ -4,8 +4,8 @@ from litex.gen.genlib.record import *
 
 def phase_cmd_description(addressbits, bankbits):
     return [
-        ("address", addressbits, DIR_M_TO_S),
-        ("bank",       bankbits, DIR_M_TO_S),
+        ("address", addressbits, DIR_M_TO_S, True),
+        ("bank",       bankbits, DIR_M_TO_S, True),
         ("cas_n",             1, DIR_M_TO_S),
         ("cs_n",              1, DIR_M_TO_S),
         ("ras_n",             1, DIR_M_TO_S),
@@ -18,16 +18,16 @@ def phase_cmd_description(addressbits, bankbits):
 
 def phase_wrdata_description(databits):
     return [
-        ("wrdata",         databits, DIR_M_TO_S),
+        ("wrdata",         databits, DIR_M_TO_S, True),
         ("wrdata_en",             1, DIR_M_TO_S),
-        ("wrdata_mask", databits//8, DIR_M_TO_S)
+        ("wrdata_mask", databits//8, DIR_M_TO_S, True)
     ]
 
 
 def phase_rddata_description(databits):
     return [
         ("rddata_en",           1, DIR_M_TO_S),
-        ("rddata",       databits, DIR_S_TO_M),
+        ("rddata",       databits, DIR_S_TO_M, True),
         ("rddata_valid",        1, DIR_S_TO_M)
     ]