From ac33d2972700d414c908f3efbbf63f260c14c5c1 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 12 May 2020 09:07:59 +0200 Subject: [PATCH] litedram_gen: simplify and expose bus when CPU is set to None. --- examples/arty.yml | 3 --- examples/genesys2.yml | 3 --- examples/nexys4ddr.yml | 2 -- examples/versa_ecp5.yml | 3 --- litedram/gen.py | 40 ++++++++++++++-------------------------- 5 files changed, 14 insertions(+), 37 deletions(-) diff --git a/examples/arty.yml b/examples/arty.yml index f69dd34..6c85d31 100644 --- a/examples/arty.yml +++ b/examples/arty.yml @@ -46,7 +46,4 @@ "depth": 0x01000000, }, }, - - # Bus Port ----------------------------------------------------------------- - "bus_expose": True, # Expose SoC bus as I/Os } diff --git a/examples/genesys2.yml b/examples/genesys2.yml index 001a4ae..bb143f1 100644 --- a/examples/genesys2.yml +++ b/examples/genesys2.yml @@ -46,7 +46,4 @@ "depth": 0x01000000, }, }, - - # Bus Port ----------------------------------------------------------------- - "bus_expose": False, # Expose SoC bus as I/Os } diff --git a/examples/nexys4ddr.yml b/examples/nexys4ddr.yml index 15d8f19..89d9b00 100644 --- a/examples/nexys4ddr.yml +++ b/examples/nexys4ddr.yml @@ -41,6 +41,4 @@ "depth": 0x01000000, }, }, - # Bus Port ----------------------------------------------------------------- - "bus_expose": False, # Expose SoC bus as I/Os } diff --git a/examples/versa_ecp5.yml b/examples/versa_ecp5.yml index bc7041e..2579bf8 100644 --- a/examples/versa_ecp5.yml +++ b/examples/versa_ecp5.yml @@ -38,7 +38,4 @@ "depth": 0x01000000, }, }, - - # Bus Port ----------------------------------------------------------------- - "bus_expose": False, # Expose SoC bus as I/Os } diff --git a/litedram/gen.py b/litedram/gen.py index 028d35f..d5dcc85 100755 --- a/litedram/gen.py +++ b/litedram/gen.py @@ -106,16 +106,6 @@ def get_dram_ios(core_config): ), ] -def get_csr_ios(aw, dw): - return [ - ("csr_port", 0, - Subsignal("adr", Pins(aw)), - Subsignal("we", Pins(1)), - Subsignal("dat_w", Pins(dw)), - Subsignal("dat_r", Pins(dw)) - ), - ] - def get_native_user_port_ios(_id, aw, dw): return [ ("user_port_{}".format(_id), 0, @@ -314,18 +304,15 @@ class LiteDRAMCore(SoCSDRAM): cpu_type = core_config["cpu"] cpu_variant = core_config.get("cpu_variant", "standard") bus_expose = core_config.get("bus_expose", False) + kwargs["l2_size"] = 0 + kwargs["min_l2_data_width"] = 0 if cpu_type is None: kwargs["integrated_rom_size"] = 0 kwargs["integrated_sram_size"] = 0 - kwargs["l2_size"] = 0 - kwargs["min_l2_data_width"] = 0 kwargs["with_uart"] = False kwargs["with_timer"] = False kwargs["with_ctrl"] = False kwargs["with_wishbone"] = False - else: - kwargs["l2_size"] = 0 - kwargs["min_l2_data_width"] = 0 # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, sys_clk_freq, @@ -371,23 +358,24 @@ class LiteDRAMCore(SoCSDRAM): sdram_module = core_config["sdram_module"](sys_clk_freq, "1:4" if core_config["memtype"] == "DDR3" else "1:2") - controller_settings = controller_settings=ControllerSettings( + controller_settings = controller_settings = ControllerSettings( cmd_buffer_depth=core_config["cmd_buffer_depth"]) self.register_sdram(self.ddrphy, geom_settings = sdram_module.geom_settings, timing_settings = sdram_module.timing_settings, controller_settings = controller_settings) - # DRAM Initialization ---------------------------------------------------------------------- - self.submodules.ddrctrl = LiteDRAMCoreControl() - self.add_csr("ddrctrl") - self.comb += [ - platform.request("init_done").eq(self.ddrctrl.init_done.storage), - platform.request("init_error").eq(self.ddrctrl.init_error.storage) - ] - - # Bus port --------------------------------------------------------------------------------- - if bus_expose: + # DRAM Control/Status ---------------------------------------------------------------------- + if cpu_type is not None: + # Expose calibration status to user. + self.submodules.ddrctrl = LiteDRAMCoreControl() + self.add_csr("ddrctrl") + self.comb += [ + platform.request("init_done").eq(self.ddrctrl.init_done.storage), + platform.request("init_error").eq(self.ddrctrl.init_error.storage) + ] + else: + # Expose bus interface to user. wb_bus = wishbone.Interface() self.bus.add_master(master=wb_bus) platform.add_extension(wb_bus.get_ios("wb"))