diff --git a/test/Makefile b/test/Makefile deleted file mode 100644 index a33e6ea..0000000 --- a/test/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -COREDIR = ../ -PYTHON = python3 - -CMD = PYTHONPATH=$(COREDIR) $(PYTHON) - -bist_tb: - $(CMD) bist_tb.py - -bist_async_tb: - $(CMD) bist_async_tb.py - -downconverter_tb: - $(CMD) downconverter_tb.py - -upconverter_tb: - $(CMD) upconverter_tb.py - -all: bist_tb bist_async_tb downconverter_tb upconverter_tb diff --git a/test/downconverter_tb.py b/test/downconverter_tb.py deleted file mode 100755 index 7b4eb57..0000000 --- a/test/downconverter_tb.py +++ /dev/null @@ -1,85 +0,0 @@ -#!/usr/bin/env python3 - -from litex.gen import * - -from litex.soc.interconnect.stream import * -from litex.soc.interconnect.stream_sim import check - -from litedram.common import LiteDRAMWritePort, LiteDRAMReadPort -from litedram.frontend.adaptation import LiteDRAMPortConverter - -from test.common import * - -class TB(Module): - def __init__(self): - self.write_user_port = LiteDRAMWritePort(aw=32, dw=64) - self.write_crossbar_port = LiteDRAMWritePort(aw=32, dw=32) - self.submodules.write_converter = LiteDRAMPortConverter(self.write_user_port, - self.write_crossbar_port) - - self.read_user_port = LiteDRAMReadPort(aw=32, dw=64) - self.read_crossbar_port = LiteDRAMReadPort(aw=32, dw=32) - self.submodules.read_converter = LiteDRAMPortConverter(self.read_user_port, - self.read_crossbar_port) - - self.memory = DRAMMemory(32, 128) - - -write_data = [seed_to_data(i, nbits=64) for i in range(8)] -read_data = [] - - -@passive -def read_generator(dut): - yield dut.read_user_port.rdata.ready.eq(1) - while True: - if (yield dut.read_user_port.rdata.valid): - read_data.append((yield dut.read_user_port.rdata.data)) - yield - - -def main_generator(dut): - # write - for i in range(8): - yield dut.write_user_port.cmd.valid.eq(1) - yield dut.write_user_port.cmd.we.eq(1) - yield dut.write_user_port.cmd.adr.eq(i) - yield dut.write_user_port.wdata.valid.eq(1) - yield dut.write_user_port.wdata.data.eq(write_data[i]) - yield - while (yield dut.write_user_port.cmd.ready) == 0: - yield - while (yield dut.write_user_port.wdata.ready) == 0: - yield - yield - - # read - yield dut.read_user_port.rdata.ready.eq(1) - for i in range(8): - yield dut.read_user_port.cmd.valid.eq(1) - yield dut.read_user_port.cmd.we.eq(0) - yield dut.read_user_port.cmd.adr.eq(i) - yield - while (yield dut.read_user_port.cmd.ready) == 0: - yield - yield dut.read_user_port.cmd.valid.eq(0) - yield - - # delay - for i in range(32): - yield - - # check - s, l, e = check(write_data, read_data) - print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e)) - -if __name__ == "__main__": - tb = TB() - generators = { - "sys" : [main_generator(tb), - read_generator(tb), - tb.memory.write_generator(tb.write_crossbar_port), - tb.memory.read_generator(tb.read_crossbar_port)] - } - clocks = {"sys": 10} - run_simulation(tb, generators, clocks, vcd_name="sim.vcd") diff --git a/test/bist_tb.py b/test/test_bist.py similarity index 90% rename from test/bist_tb.py rename to test/test_bist.py index e4d85f6..1ffe986 100755 --- a/test/bist_tb.py +++ b/test/test_bist.py @@ -1,5 +1,4 @@ -#!/usr/bin/env python3 - +import unittest import random from litex.gen import * @@ -13,12 +12,13 @@ from litedram.frontend.bist import LiteDRAMBISTCheckerScope from test.common import * -class TB(Module): + +class DUT(Module): def __init__(self): self.write_port = LiteDRAMWritePort(aw=32, dw=32) self.read_port = LiteDRAMReadPort(aw=32, dw=32) - self.submodules.generator = LiteDRAMBISTGenerator(self.write_port, random=True) - self.submodules.checker = LiteDRAMBISTChecker(self.read_port, random=True) + self.submodules.generator = LiteDRAMBISTGenerator(self.write_port, True) + self.submodules.checker = LiteDRAMBISTChecker(self.read_port, True) self.submodules.checker_scope = LiteDRAMBISTCheckerScope(self.checker) @@ -169,15 +169,16 @@ def main_generator(dut, mem): yield -if __name__ == "__main__": - tb = TB() - mem = DRAMMemory(32, 128) - generators = { - "sys" : [ - main_generator(tb, mem), - mem.write_generator(tb.write_port), - mem.read_generator(tb.read_port), - ], - } - clocks = {"sys": 10} - run_simulation(tb, generators, clocks, vcd_name="sim.vcd") +class TestBIST(unittest.TestCase): + def test(self): + dut = DUT() + mem = DRAMMemory(32, 128) + generators = { + "sys" : [ + main_generator(dut, mem), + mem.write_generator(dut.write_port), + mem.read_generator(dut.read_port) + ] + } + clocks = {"sys": 10} + run_simulation(dut, generators, clocks, vcd_name="sim.vcd") diff --git a/test/bist_async_tb.py b/test/test_bist_async.py similarity index 82% rename from test/bist_async_tb.py rename to test/test_bist_async.py index 3930f50..e58cafa 100755 --- a/test/bist_async_tb.py +++ b/test/test_bist_async.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python3 +import unittest from litex.gen import * @@ -47,7 +47,9 @@ class TB(Module): read_latency=4, write_latency=0 ) - self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings, we_granularity=0) + self.submodules.sdrphy = SDRAMPHYModel(sdram_module, + phy_settings, + we_granularity=0) # controller self.submodules.controller = LiteDRAMController( @@ -59,7 +61,7 @@ class TB(Module): self.submodules.crossbar = LiteDRAMCrossbar(self.controller.interface, self.controller.nrowbits) - # write port + # ports write_user_port = self.crossbar.get_port("write", cd="write") read_user_port = self.crossbar.get_port("read", cd="read") @@ -71,9 +73,11 @@ class TB(Module): def main_generator(dut): for i in range(100): yield + # init yield from reset_bist_module(dut.generator) yield from reset_bist_module(dut.checker) + # write yield dut.generator.base.storage.eq(16) yield dut.generator.length.storage.eq(16) @@ -84,6 +88,7 @@ def main_generator(dut): yield while((yield dut.generator.done.status) == 0): yield + # read yield dut.checker.base.storage.eq(16) yield dut.checker.length.storage.eq(16) @@ -94,16 +99,14 @@ def main_generator(dut): yield while((yield dut.checker.done.status) == 0): yield - # check - print("errors {:d}".format((yield dut.checker.error_count.status))) - yield -if __name__ == "__main__": - tb = TB() - generators = { - "sys" : [main_generator(tb)] - } - clocks = {"sys": 10, - "write": 12, - "read": 8} - run_simulation(tb, generators, clocks, vcd_name="sim.vcd") + +class TestBISTAsync(unittest.TestCase): + def test(self): + tb = TB() + generators = {"sys" : [main_generator(tb)]} + clocks = {"sys": 10, + "write": 12, + "read": 8} + run_simulation(tb, generators, clocks, vcd_name="sim.vcd") + self.assertEqual(dut.checker.error_count.status, 0) diff --git a/test/test_downconverter.py b/test/test_downconverter.py new file mode 100755 index 0000000..7883952 --- /dev/null +++ b/test/test_downconverter.py @@ -0,0 +1,91 @@ +import unittest + +from litex.gen import * + +from litex.soc.interconnect.stream import * + +from litedram.common import LiteDRAMWritePort, LiteDRAMReadPort +from litedram.frontend.adaptation import LiteDRAMPortConverter + +from test.common import * + + +class DUT(Module): + def __init__(self): + # write port and converter + self.write_user_port = LiteDRAMWritePort(aw=32, dw=64) + self.write_crossbar_port = LiteDRAMWritePort(aw=32, dw=32) + write_converter = LiteDRAMPortConverter(self.write_user_port, + self.write_crossbar_port) + self.submodules += write_converter + + # read port and converter + self.read_user_port = LiteDRAMReadPort(aw=32, dw=64) + self.read_crossbar_port = LiteDRAMReadPort(aw=32, dw=32) + read_converter = LiteDRAMPortConverter(self.read_user_port, + self.read_crossbar_port) + self.submodules += read_converter + + # memory + self.memory = DRAMMemory(32, 128) + + +write_data = [seed_to_data(i, nbits=64) for i in range(8)] +read_data = [] + + +@passive +def read_generator(read_port): + yield read_port.rdata.ready.eq(1) + while True: + if (yield read_port.rdata.valid): + read_data.append((yield read_port.rdata.data)) + yield + + +def main_generator(write_port, read_port): + # write + for i in range(8): + yield write_port.cmd.valid.eq(1) + yield write_port.cmd.we.eq(1) + yield write_port.cmd.adr.eq(i) + yield write_port.wdata.valid.eq(1) + yield write_port.wdata.data.eq(write_data[i]) + yield + while (yield write_port.cmd.ready) == 0: + yield + while (yield write_port.wdata.ready) == 0: + yield + yield + + # read + yield read_port.rdata.ready.eq(1) + for i in range(8): + yield read_port.cmd.valid.eq(1) + yield read_port.cmd.we.eq(0) + yield read_port.cmd.adr.eq(i) + yield + while (yield read_port.cmd.ready) == 0: + yield + yield read_port.cmd.valid.eq(0) + yield + + # latency delay + for i in range(32): + yield + + +class TestDownConverter(unittest.TestCase): + def test(self): + dut = DUT() + generators = { + "sys" : [ + main_generator(dut.write_user_port, dut.read_user_port), + read_generator(dut.read_user_port), + dut.memory.write_generator(dut.write_crossbar_port), + dut.memory.read_generator(dut.read_crossbar_port) + ] + } + clocks = {"sys": 10} + run_simulation(dut, generators, clocks, vcd_name="sim.vcd") + self.assertEqual(write_data, read_data) diff --git a/test/test_upconverter.py b/test/test_upconverter.py new file mode 100755 index 0000000..8258947 --- /dev/null +++ b/test/test_upconverter.py @@ -0,0 +1,94 @@ +import unittest + +from litex.gen import * + +from litex.soc.interconnect.stream import * + +from litedram.common import LiteDRAMWritePort, LiteDRAMReadPort +from litedram.frontend.adaptation import LiteDRAMPortConverter + +from test.common import * + + +class DUT(Module): + def __init__(self): + # write port and converter + self.write_user_port = LiteDRAMWritePort(aw=32, dw=32) + self.write_crossbar_port = LiteDRAMWritePort(aw=32, dw=128) + write_converter = LiteDRAMPortConverter(self.write_user_port, + self.write_crossbar_port) + self.submodules += write_converter + + # read port and converter + self.read_user_port = LiteDRAMReadPort(aw=32, dw=32) + self.read_crossbar_port = LiteDRAMReadPort(aw=32, dw=128) + read_converter = LiteDRAMPortConverter(self.read_user_port, + self.read_crossbar_port) + self.submodules += read_converter + + # memory + self.memory = DRAMMemory(128, 128) + + +write_data = [seed_to_data(i, nbits=32) for i in range(16)] +read_data = [] + + +@passive +def read_generator(read_port): + yield read_port.rdata.ready.eq(1) + while True: + if (yield read_port.rdata.valid): + read_data.append((yield read_port.rdata.data)) + yield + + +def main_generator(write_port, read_port): + # write + for i in range(16): + yield write_port.cmd.valid.eq(1) + yield write_port.cmd.we.eq(1) + yield write_port.cmd.adr.eq(i) + yield + while (yield write_port.cmd.ready) == 0: + yield + yield write_port.cmd.valid.eq(0) + yield + yield write_port.wdata.valid.eq(1) + yield write_port.wdata.data.eq(write_data[i]) + yield + while (yield write_port.wdata.ready) == 0: + yield + yield write_port.wdata.valid.eq(0) + yield + + # read + for i in range(16): + yield read_port.cmd.valid.eq(1) + yield read_port.cmd.we.eq(0) + yield read_port.cmd.adr.eq(i) + yield + while (yield read_port.cmd.ready) == 0: + yield + yield read_port.cmd.valid.eq(0) + yield + + # delay + for i in range(32): + yield + + +class TestUpConverter(unittest.TestCase): + def test(self): + dut = DUT() + generators = { + "sys" : [ + main_generator(dut.write_user_port, dut.read_user_port), + read_generator(dut.read_user_port), + dut.memory.write_generator(dut.write_crossbar_port), + dut.memory.read_generator(dut.read_crossbar_port) + ] + } + clocks = {"sys": 10} + run_simulation(dut, generators, clocks, vcd_name="sim.vcd") + self.assertEqual(write_data, read_data) diff --git a/test/upconverter_tb.py b/test/upconverter_tb.py deleted file mode 100755 index 6b759c0..0000000 --- a/test/upconverter_tb.py +++ /dev/null @@ -1,89 +0,0 @@ -#!/usr/bin/env python3 - -from litex.gen import * - -from litex.soc.interconnect.stream import * -from litex.soc.interconnect.stream_sim import check - -from litedram.common import LiteDRAMWritePort, LiteDRAMReadPort -from litedram.frontend.adaptation import LiteDRAMPortConverter - -from test.common import * - -class TB(Module): - def __init__(self): - self.write_user_port = LiteDRAMWritePort(aw=32, dw=32) - self.write_crossbar_port = LiteDRAMWritePort(aw=32, dw=128) - self.submodules.write_converter = LiteDRAMPortConverter(self.write_user_port, - self.write_crossbar_port) - - self.read_user_port = LiteDRAMReadPort(aw=32, dw=32) - self.read_crossbar_port = LiteDRAMReadPort(aw=32, dw=128) - self.submodules.read_converter = LiteDRAMPortConverter(self.read_user_port, - self.read_crossbar_port) - - self.memory = DRAMMemory(128, 128) - - -write_data = [seed_to_data(i, nbits=32) for i in range(16)] -read_data = [] - - -@passive -def read_generator(dut): - yield dut.read_user_port.rdata.ready.eq(1) - while True: - if (yield dut.read_user_port.rdata.valid): - read_data.append((yield dut.read_user_port.rdata.data)) - yield - - -def main_generator(dut): - # write - for i in range(16): - yield dut.write_user_port.cmd.valid.eq(1) - yield dut.write_user_port.cmd.we.eq(1) - yield dut.write_user_port.cmd.adr.eq(i) - yield - while (yield dut.write_user_port.cmd.ready) == 0: - yield - yield dut.write_user_port.cmd.valid.eq(0) - yield - yield dut.write_user_port.wdata.valid.eq(1) - yield dut.write_user_port.wdata.data.eq(write_data[i]) - yield - while (yield dut.write_user_port.wdata.ready) == 0: - yield - yield dut.write_user_port.wdata.valid.eq(0) - yield - - # read - for i in range(16): - yield dut.read_user_port.cmd.valid.eq(1) - yield dut.read_user_port.cmd.we.eq(0) - yield dut.read_user_port.cmd.adr.eq(i) - yield - while (yield dut.read_user_port.cmd.ready) == 0: - yield - yield dut.read_user_port.cmd.valid.eq(0) - yield - - # delay - for i in range(32): - yield - - # check - s, l, e = check(write_data, read_data) - print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e)) - - -if __name__ == "__main__": - tb = TB() - generators = { - "sys" : [main_generator(tb), - read_generator(tb), - tb.memory.write_generator(tb.write_crossbar_port), - tb.memory.read_generator(tb.read_crossbar_port)] - } - clocks = {"sys": 10} - run_simulation(tb, generators, clocks, vcd_name="sim.vcd")