diff --git a/litedram/gen.py b/litedram/gen.py
index 7750a89..e577dc4 100644
--- a/litedram/gen.py
+++ b/litedram/gen.py
@@ -290,7 +290,9 @@ class LiteDRAMCore(SoCSDRAM):
 
         # CSR port
         if core_config.get("expose_csr_port", "no") == "yes":
-            csr_port = csr_bus.Interface(self.csr_address_width, self.csr_data_width)
+            csr_port = csr_bus.Interface(
+                address_width=self.csr_address_width,
+                data_width=self.csr_data_width)
             self.add_csr_master(csr_port)
             platform.add_extension(get_csr_ios(self.csr_address_width,
                                                self.csr_data_width))