From afbf7097674b1698ab0333a9de9a50dc59c3e1fd Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Mon, 23 Sep 2019 08:50:25 +0200 Subject: [PATCH] We had the address and data bus sizes mixed up Signed-off-by: Benjamin Herrenschmidt --- litedram/gen.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/litedram/gen.py b/litedram/gen.py index 7750a89..e577dc4 100644 --- a/litedram/gen.py +++ b/litedram/gen.py @@ -290,7 +290,9 @@ class LiteDRAMCore(SoCSDRAM): # CSR port if core_config.get("expose_csr_port", "no") == "yes": - csr_port = csr_bus.Interface(self.csr_address_width, self.csr_data_width) + csr_port = csr_bus.Interface( + address_width=self.csr_address_width, + data_width=self.csr_data_width) self.add_csr_master(csr_port) platform.add_extension(get_csr_ios(self.csr_address_width, self.csr_data_width))