diff --git a/litedram/phy/s7ddrphy.py b/litedram/phy/s7ddrphy.py
index f78af86..eda66ab 100644
--- a/litedram/phy/s7ddrphy.py
+++ b/litedram/phy/s7ddrphy.py
@@ -50,10 +50,12 @@ class S7DDRPHY(Module, AutoCSR):
         }
         half_sys8x_taps = math.floor(tck/(4*iodelay_tap_average[iodelay_clk_freq]))
 
-        cl, cwl         = get_cl_cw(memtype, tck)
-        cl_sys_latency  = get_sys_latency(nphases, cl)
-        cwl             = cwl + cmd_latency
-        cwl_sys_latency = get_sys_latency(nphases, cwl)
+        cl, cwl             = get_cl_cw(memtype, tck)
+        cl_sys_latency      = get_sys_latency(nphases, cl)
+        cwl                 = cwl + cmd_latency
+        cwl_sys_latency     = get_sys_latency(nphases, cwl)
+        rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency,   cl)
+        wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl)
 
         # Registers --------------------------------------------------------------------------------
         self._rst             = CSRStorage()
@@ -81,9 +83,17 @@ class S7DDRPHY(Module, AutoCSR):
             self._wdly_dqs_rst  = CSR()
             self._wdly_dqs_inc  = CSR()
 
+        self._rdphase = CSRStorage(2, reset=rdphase)
+        self._wrphase = CSRStorage(2, reset=wrphase)
+
         # PHY settings -----------------------------------------------------------------------------
-        rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl)
-        wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl)
+        _rdphase    = self._rdphase.storage
+        _wrphase    = self._wrphase.storage
+        _rdcmdphase = Signal(2)
+        _wrcmdphase = Signal(2)
+        self.comb += _rdcmdphase.eq(_rdphase - 1)
+        self.comb += _wrcmdphase.eq(_wrphase - 1)
+
         self.settings = PhySettings(
             phytype       = phytype,
             memtype       = memtype,
@@ -91,13 +101,13 @@ class S7DDRPHY(Module, AutoCSR):
             dfi_databits  = 2*databits,
             nranks        = nranks,
             nphases       = nphases,
-            rdphase       = rdphase,
-            wrphase       = wrphase,
-            rdcmdphase    = rdcmdphase,
-            wrcmdphase    = wrcmdphase,
+            rdphase       = _rdphase,
+            wrphase       = _wrphase,
+            rdcmdphase    = _rdcmdphase,
+            wrcmdphase    = _wrcmdphase,
             cl            = cl,
             cwl           = cwl - cmd_latency,
-            read_latency  = 2 + cl_sys_latency + 2 + 2,
+            read_latency  = cl_sys_latency + 6,
             write_latency = cwl_sys_latency,
             cmd_latency   = cmd_latency,
             cmd_delay     = cmd_delay,