From b0382e877655b282f7065614f4302a6c9ff889ac Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 13 Jun 2016 14:41:57 +0200
Subject: [PATCH] frontend/crossbar: add clock domain crossing and data width
 convertion to get_port

---
 litedram/frontend/crossbar.py | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/litedram/frontend/crossbar.py b/litedram/frontend/crossbar.py
index 9301ce7..5412b7d 100644
--- a/litedram/frontend/crossbar.py
+++ b/litedram/frontend/crossbar.py
@@ -7,6 +7,7 @@ from litex.gen.genlib import roundrobin
 from litex.soc.interconnect import stream
 
 from litedram.common import *
+from litedram.frontend.adaptation import LiteDRAMPortCDC, LiteDRAMPortConverter
 
 
 class LiteDRAMCrossbar(Module):
@@ -25,11 +26,32 @@ class LiteDRAMCrossbar(Module):
 
         self.masters = []
 
-    def get_port(self):
+    def get_port(self, dw=None, cd="sys"):
         if self.finalized:
             raise FinalizeError
-        port = LiteDRAMPort(self.rca_bits + self.bank_bits, self.dw)
+        if dw is None:
+            dw = self.dw
+
+        # crossbar port
+        port = LiteDRAMPort(self.rca_bits + self.bank_bits, self.dw, "sys")
         self.masters.append(port)
+
+        # clock domain crossing
+        if cd != "sys":
+            new_port = LiteDRAMPort(port.aw, port.dw, cd)
+            self.submodules += LiteDRAMPortCDC(new_port, port)
+            port = new_port
+
+        # data width convertion
+        if dw != self.dw:
+            if dw > self.dw:
+                adr_shift = log2_int(dw//self.dw)
+            else:
+                adr_shift = -log2_int(self.dw//dw)
+            new_port = LiteDRAMPort(port.aw + adr_shift, dw, cd=cd)
+            self.submodules += ClockDomainsRenamer(cd)(LiteDRAMPortConverter(new_port, port))
+            port = new_port
+
         return port
 
     def do_finalize(self):