From 7238a9c0e2b519296c0c04c41a1464cd76afc170 Mon Sep 17 00:00:00 2001
From: Piotr Binkowski <pbinkowski@antmicro.com>
Date: Thu, 26 Mar 2020 16:18:16 +0100
Subject: [PATCH] modules: add MTA4ATF51264HZ DDR4 SO-DIMM

---
 litedram/modules.py | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/litedram/modules.py b/litedram/modules.py
index b8bde9d..addc1b8 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -612,3 +612,20 @@ class KVR21SE15S84(SDRAMModule):
         "2133": _SpeedgradeTimings(tRP=13.5, tRCD=13.5, tWR=15, tRFC=trfc, tFAW=(20, 25), tRAS=33),
     }
     speedgrade_timings["default"] = speedgrade_timings["2133"]
+
+class MTA4ATF51264HZ(SDRAMModule):
+    memtype = "DDR4"
+    # geometry
+    ngroupbanks = 4
+    ngroups     = 2
+    nbanks      = ngroups * ngroupbanks
+    nrows       = 65536
+    ncols       = 1024
+    # timings
+    trefi = {"1x": 64e6/8192,   "2x": (64e6/8192)/2, "4x": (64e6/8192)/4}
+    trfc  = {"1x": (None, 350), "2x": (None, 260),   "4x": (None, 160)}
+    technology_timings = _TechnologyTimings(tREFI=trefi, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 4.9), tZQCS=(128, 80))
+    speedgrade_timings = {
+        "2133": _SpeedgradeTimings(tRP=13.5, tRCD=13.5, tWR=15, tRFC=trfc, tFAW=(20, 25), tRAS=33),
+    }
+    speedgrade_timings["default"] = speedgrade_timings["2133"]