From b0bde294c0a440116292a4267e6a33cf73edc7ad Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?J=C4=99drzej=20Boczar?= <jboczar@antmicro.com>
Date: Wed, 13 May 2020 10:14:00 +0200
Subject: [PATCH] frontend/wishbone: fix wb2native missing wdata.ready when
 wb/port data widths differ

---
 litedram/frontend/wishbone.py | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/litedram/frontend/wishbone.py b/litedram/frontend/wishbone.py
index a8f8e82..05eb468 100644
--- a/litedram/frontend/wishbone.py
+++ b/litedram/frontend/wishbone.py
@@ -28,16 +28,16 @@ class LiteDRAMWishbone2Native(Module):
             [("data", port_data_width),     ("we", port_data_width//8)],
         )
         self.submodules += wdata_converter
-        wdata_lock = Signal()
+        wdata_complete = Signal()
         self.comb += [
-            wdata_converter.sink.valid.eq(wishbone.cyc & wishbone.stb & wishbone.we & ~wdata_lock),
+            wdata_converter.sink.valid.eq(wishbone.cyc & wishbone.stb & wishbone.we & ~wdata_complete),
             wdata_converter.sink.data.eq(wishbone.dat_w),
             wdata_converter.sink.we.eq(wishbone.sel),
             wdata_converter.source.connect(port.wdata)
         ]
         self.sync += [
             If(wdata_converter.sink.valid & wdata_converter.sink.ready,
-               wdata_lock.eq(1)
+               wdata_complete.eq(1)
             )
         ]
 
@@ -75,9 +75,9 @@ class LiteDRAMWishbone2Native(Module):
             )
         )
         fsm.act("WAIT-WRITE",
-            If(wdata_converter.sink.ready,
-                NextValue(wdata_lock, 0),
-                wishbone.ack.eq(1),
+            If(wdata_complete,
+               wishbone.ack.eq(1),
+                NextValue(wdata_complete, 0),
                 NextState("CMD")
             )
         )