From b145b0c338f170dbc3b2eaf2727a10bb4b529de8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 18 Sep 2018 15:24:41 +0200 Subject: [PATCH] frontend/axi: fix write response implementation --- litedram/frontend/axi.py | 15 +++++++++------ test/test_axi.py | 1 + 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/litedram/frontend/axi.py b/litedram/frontend/axi.py index 45323cf..e632533 100644 --- a/litedram/frontend/axi.py +++ b/litedram/frontend/axi.py @@ -10,7 +10,6 @@ Features: - ID support (configurable width). Limitations: -- Write response always supposed to be ready. - Response always okay. - No reordering. """ @@ -164,14 +163,18 @@ class LiteDRAMAXI2NativeW(Module): # Write ID Buffer & Response id_buffer = stream.SyncFIFO([("id", axi.id_width)], buffer_depth) - self.submodules += id_buffer + resp_buffer = stream.SyncFIFO([("id", axi.id_width), ("resp", 2)], buffer_depth) + self.submodules += id_buffer, resp_buffer self.comb += [ id_buffer.sink.valid.eq(aw.valid & aw.ready), id_buffer.sink.id.eq(aw.id), - axi.b.valid.eq(axi.w.valid & axi.w.ready), # Note: Write response always supposed to be ready. - axi.b.resp.eq(resp_types["okay"]), - axi.b.id.eq(id_buffer.source.id), - id_buffer.source.ready.eq(axi.b.valid & axi.b.ready) + If(axi.w.valid & axi.w.last & axi.w.ready, + resp_buffer.sink.valid.eq(1), + resp_buffer.sink.resp.eq(resp_types["okay"]), + resp_buffer.sink.id.eq(id_buffer.source.id), + id_buffer.source.ready.eq(1) + ), + resp_buffer.source.connect(axi.b) ] # Command diff --git a/test/test_axi.py b/test/test_axi.py index f6aeafb..3f71fdc 100755 --- a/test/test_axi.py +++ b/test/test_axi.py @@ -38,6 +38,7 @@ class TestAXI(unittest.TestCase): yield # send data yield axi_port.w.valid.eq(1) + yield axi_port.w.last.eq(1) yield axi_port.w.data.eq(write.data) yield while (yield axi_port.w.ready) == 0: