From b24943e6919c0d9b284d3d67266c353628371370 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 8 Oct 2020 16:21:02 +0200
Subject: [PATCH] bench/genesys2: add litescope on ddrphy.dfi.

---
 bench/genesys2.py | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/bench/genesys2.py b/bench/genesys2.py
index 3d5cb75..7d9a6ac 100755
--- a/bench/genesys2.py
+++ b/bench/genesys2.py
@@ -97,6 +97,15 @@ class BenchSoC(SoCCore):
         self.add_csr("ethphy")
         self.add_etherbone(phy=self.ethphy)
 
+        # Analyzer ---------------------------------------------------------------------------------
+        from litescope import LiteScopeAnalyzer
+        analyzer_signals = [self.ddrphy.dfi]
+        self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
+            depth        = 512,
+            clock_domain = "sys",
+            csr_csv      = "analyzer.csv")
+        self.add_csr("analyzer")
+
         # Leds -------------------------------------------------------------------------------------
         from litex.soc.cores.led import LedChaser
         self.submodules.leds = LedChaser(