From b3ce582891f96187af5926fa7c90f0b052a7f6b0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?J=C4=99drzej=20Boczar?= <jboczar@antmicro.com>
Date: Fri, 29 Jan 2021 12:49:19 +0100
Subject: [PATCH] test: update ddr3 and ddr4 reference headers to new MR_WLVL
 defines

---
 test/reference/ddr3_init.h | 4 +++-
 test/reference/ddr4_init.h | 4 +++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/test/reference/ddr3_init.h b/test/reference/ddr3_init.h
index 6a1a209..cf88de7 100644
--- a/test/reference/ddr3_init.h
+++ b/test/reference/ddr3_init.h
@@ -70,7 +70,9 @@ const unsigned long sdram_dfii_pix_rddata_addr[SDRAM_PHY_PHASES] = {
 	CSR_SDRAM_DFII_PI3_RDDATA_ADDR
 };
 
-#define DDRX_MR1 6
+#define DDRX_MR_WRLVL_ADDRESS 1
+#define DDRX_MR_WRLVL_RESET 6
+#define DDRX_MR_WRLVL_BIT 7
 
 static void init_sequence(void)
 {
diff --git a/test/reference/ddr4_init.h b/test/reference/ddr4_init.h
index 54391d0..a87768f 100644
--- a/test/reference/ddr4_init.h
+++ b/test/reference/ddr4_init.h
@@ -71,7 +71,9 @@ const unsigned long sdram_dfii_pix_rddata_addr[SDRAM_PHY_PHASES] = {
 	CSR_SDRAM_DFII_PI3_RDDATA_ADDR
 };
 
-#define DDRX_MR1 769
+#define DDRX_MR_WRLVL_ADDRESS 1
+#define DDRX_MR_WRLVL_RESET 769
+#define DDRX_MR_WRLVL_BIT 7
 
 static void init_sequence(void)
 {