From b6a0eff2d9ce956f73a85cd34b92e918cf4d069b Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 3 Sep 2019 12:44:07 +0200
Subject: [PATCH] frontend/wishbone: split control/data paths (to avoid data
 muxes)

---
 litedram/frontend/wishbone.py | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/litedram/frontend/wishbone.py b/litedram/frontend/wishbone.py
index 129de31..81473b0 100644
--- a/litedram/frontend/wishbone.py
+++ b/litedram/frontend/wishbone.py
@@ -11,10 +11,10 @@ class LiteDRAMWishbone2Native(Module):
 
         # # #
 
+        # Control
         self.submodules.fsm = fsm = FSM(reset_state="CMD")
         fsm.act("CMD",
             port.cmd.valid.eq(wishbone.cyc & wishbone.stb),
-            port.cmd.addr.eq(wishbone.adr),
             port.cmd.we.eq(wishbone.we),
             If(port.cmd.valid & port.cmd.ready,
                 If(wishbone.we,
@@ -26,8 +26,6 @@ class LiteDRAMWishbone2Native(Module):
         )
         fsm.act("WRITE",
             port.wdata.valid.eq(1),
-            port.wdata.we.eq(wishbone.sel),
-            port.wdata.data.eq(wishbone.dat_w),
             If(port.wdata.ready,
                 wishbone.ack.eq(1),
                 NextState("CMD")
@@ -36,12 +34,22 @@ class LiteDRAMWishbone2Native(Module):
         fsm.act("READ",
             port.rdata.ready.eq(1),
             If(port.rdata.valid,
-                wishbone.dat_r.eq(port.rdata.data),
                 wishbone.ack.eq(1),
                 NextState("CMD")
             )
         )
 
+        # Datapath
+        self.comb += [
+            # cmd
+            port.cmd.addr.eq(wishbone.adr),
+            # write
+            port.wdata.we.eq(wishbone.sel),
+            port.wdata.data.eq(wishbone.dat_w),
+            # read
+            wishbone.dat_r.eq(port.rdata.data),
+        ]
+
 
 class LiteDRAMWishbone2AXI(Module):
     def __init__(self, wishbone, port):