From b71ed354ad3b184ce7e3f29bbf4e2e480459c41e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 15 Oct 2018 08:34:41 +0200 Subject: [PATCH] core/bankmachine: manage tRC --- litedram/core/bankmachine.py | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/litedram/core/bankmachine.py b/litedram/core/bankmachine.py index b9bee94..ab74b5f 100644 --- a/litedram/core/bankmachine.py +++ b/litedram/core/bankmachine.py @@ -89,6 +89,10 @@ class BankMachine(Module): self.submodules.twtpcon = twtpcon = tXXDController(precharge_time) self.comb += twtpcon.valid.eq(cmd.valid & cmd.ready & cmd.is_write) + # Respect tRC activate-activate time + self.submodules.trccon = trccon = tXXDController(settings.timing.tRC) + self.comb += trccon.valid.eq(cmd.valid & cmd.ready & track_open) + # Respect tRAS activate-precharge time self.submodules.trascon = trascon = tXXDController(settings.timing.tRAS) self.comb += trascon.valid.eq(cmd.valid & cmd.ready & track_open) @@ -153,14 +157,16 @@ class BankMachine(Module): track_close.eq(1) ) fsm.act("ACTIVATE", - sel_row_addr.eq(1), - track_open.eq(1), - cmd.valid.eq(1), - cmd.is_cmd.eq(1), - If(cmd.ready, - NextState("TRCD") - ), - cmd.ras.eq(1) + If(trccon.ready, + sel_row_addr.eq(1), + track_open.eq(1), + cmd.valid.eq(1), + cmd.is_cmd.eq(1), + If(cmd.ready, + NextState("TRCD") + ), + cmd.ras.eq(1) + ) ) fsm.act("REFRESH", If(twtpcon.ready,