From 89581c1da71de07f29bebba541b8c4ff629eee44 Mon Sep 17 00:00:00 2001 From: Michal Sieron Date: Tue, 10 Jan 2023 18:27:47 +0100 Subject: [PATCH 1/4] gen: increase ROM size Signed-off-by: Michal Sieron --- litedram/gen.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litedram/gen.py b/litedram/gen.py index 866e462..6efd02b 100755 --- a/litedram/gen.py +++ b/litedram/gen.py @@ -856,7 +856,7 @@ def main(): builder_arguments = builder_argdict(args) builder_arguments["compile_gateware"] = False - soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x8000) + soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0xC000) builder = Builder(soc, **builder_arguments) builder.build(build_name=args.name, regular_comb=False) From f466c5f1dbeb37c4dde8471c5422ce6d2175c414 Mon Sep 17 00:00:00 2001 From: Michal Sieron Date: Wed, 11 Jan 2023 14:19:31 +0100 Subject: [PATCH 2/4] frontend/bist: replicate LFSR output to fill DRAM port Signed-off-by: Michal Sieron --- litedram/frontend/bist.py | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/litedram/frontend/bist.py b/litedram/frontend/bist.py index 099887f..3414e91 100644 --- a/litedram/frontend/bist.py +++ b/litedram/frontend/bist.py @@ -8,6 +8,7 @@ """Built In Self Test (BIST) modules for testing LiteDRAM functionality.""" from functools import reduce +from math import ceil from operator import xor from migen import * @@ -211,7 +212,12 @@ class _LiteDRAMBISTGenerator(Module): raise NotImplementedError self.comb += dma_sink_addr.eq(self.base[ashift:] + (addr_gen.o & addr_mask)) - self.comb += dma.sink.data.eq(data_gen.o) + self.comb += dma.sink.data.eq( + Replicate( + data_gen.o, + ceil(dram_port.data_width / len(data_gen.o)), + )[:dram_port.data_width], + ) @ResetInserter() @@ -511,7 +517,10 @@ class _LiteDRAMBISTChecker(Module, AutoCSR): If(dma.source.valid, data_gen.ce.eq(1), NextValue(data_counter, data_counter + 1), - If(dma.source.data != data_gen.o[:min(len(data_gen.o), dram_port.data_width)], + If(dma.source.data != Replicate( + data_gen.o, + ceil(dram_port.data_width / len(data_gen.o)), + )[:dram_port.data_width], NextValue(self.errors, self.errors + 1) ), If(data_counter == (self.length[ashift:] - 1), From 73c3ec6b68ec08d2b0f21323cbf1a463ff5232aa Mon Sep 17 00:00:00 2001 From: Michal Sieron Date: Wed, 11 Jan 2023 14:39:54 +0100 Subject: [PATCH 3/4] frontend/bist: make LFSR output comb Otherwise first output after reset is 0. Signed-off-by: Michal Sieron --- litedram/frontend/bist.py | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/litedram/frontend/bist.py b/litedram/frontend/bist.py index 3414e91..c7dee9d 100644 --- a/litedram/frontend/bist.py +++ b/litedram/frontend/bist.py @@ -52,10 +52,8 @@ class LFSR(Module): curval.insert(0, nv) curval.pop() - self.sync += [ - state.eq(Cat(*curval[:n_state])), - self.o.eq(Cat(*curval)) - ] + self.sync += state.eq(Cat(*curval[:n_state])) + self.comb += self.o.eq(Cat(*curval)) # Counter ------------------------------------------------------------------------------------------ From dad2c972f775d6c3c227a0a2cc88301ebcc66ebf Mon Sep 17 00:00:00 2001 From: Michal Sieron Date: Wed, 11 Jan 2023 17:13:52 +0100 Subject: [PATCH 4/4] test/common: fix expected data for test_bist.py Expected data needs to be replicated to fill given data_width. Signed-off-by: Michal Sieron --- test/common.py | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/test/common.py b/test/common.py index 58f81d1..9e52aa3 100644 --- a/test/common.py +++ b/test/common.py @@ -354,6 +354,21 @@ class MemoryTestDataMixin: ) expected = data["32bit_long_sequential"]["expected"] expected[16//4:(16 + 64)//4] = list(range(64//4)) + + lfsr_out_width = 31 + # replicate LFSR output to fill the data_width + for test_case, config in data.items(): + expected = config["expected"] + + # extract data width from test case name + data_width = int(test_case.split("bit")[0]) + + for i, value in enumerate(expected): + for _ in range(data_width, lfsr_out_width - 1, -lfsr_out_width): + value |= value << lfsr_out_width + value &= (1 << data_width) - 1 + expected[i] = value + return data @property