diff --git a/litedram/modules.py b/litedram/modules.py
index 349b5b2..74b7639 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -375,6 +375,7 @@ class K4B2G1646F(SDRAMModule):
     }
     speedgrade_timings["default"] = speedgrade_timings["1600"]
 
+
 class H5TC4G63CFR(SDRAMModule):
     memtype = "DDR3"
     # geometry
@@ -384,7 +385,7 @@ class H5TC4G63CFR(SDRAMModule):
     # timings
     technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 7.5), tZQCS=(64, 80))
     speedgrade_timings = {
-        "800":  _SpeedgradeTimings(tRP=15,     tRCD=15,     tWR=15, tRFC=(260, None), tFAW=(None, 40), tRAS=37.5),
+        "800":  _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(260, None), tFAW=(None, 40), tRAS=37.5),
     }
     speedgrade_timings["default"] = speedgrade_timings["800"]