From b77af48d50a05b61c20854036e71786790d79d6e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 13 Jan 2020 17:05:46 +0100 Subject: [PATCH] modules/H5TC4G63CFR: cleanup --- litedram/modules.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litedram/modules.py b/litedram/modules.py index 349b5b2..74b7639 100644 --- a/litedram/modules.py +++ b/litedram/modules.py @@ -375,6 +375,7 @@ class K4B2G1646F(SDRAMModule): } speedgrade_timings["default"] = speedgrade_timings["1600"] + class H5TC4G63CFR(SDRAMModule): memtype = "DDR3" # geometry @@ -384,7 +385,7 @@ class H5TC4G63CFR(SDRAMModule): # timings technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 7.5), tZQCS=(64, 80)) speedgrade_timings = { - "800": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(260, None), tFAW=(None, 40), tRAS=37.5), + "800": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(260, None), tFAW=(None, 40), tRAS=37.5), } speedgrade_timings["default"] = speedgrade_timings["800"]