diff --git a/litedram/init.py b/litedram/init.py
index 1b32f7f..2456822 100644
--- a/litedram/init.py
+++ b/litedram/init.py
@@ -745,10 +745,10 @@ __attribute__((unused)) static inline void command_p{n}(int cmd)
     # Write/Read functions
     pix_addr_fmt = """
 static inline unsigned long {name}(int phase){{
-\tswitch (phase) {{
-\t\t{cases}
-\t\tdefault: return 0;
-\t}}
+    switch (phase) {{
+        {cases}
+        default: return 0;
+        }}
 }}
     """
     get_cases = lambda addrs: ["case {}: return {};".format(i, addr) for i, addr in enumerate(addrs)]
diff --git a/test/reference/ddr3_init.h b/test/reference/ddr3_init.h
index ac3e5c4..509b6d3 100644
--- a/test/reference/ddr3_init.h
+++ b/test/reference/ddr3_init.h
@@ -34,22 +34,22 @@
 
 static void cdelay(int i);
 
-__attribute__((unused)) static void command_p0(int cmd)
+__attribute__((unused)) static inline void command_p0(int cmd)
 {
     sdram_dfii_pi0_command_write(cmd);
     sdram_dfii_pi0_command_issue_write(1);
 }
-__attribute__((unused)) static void command_p1(int cmd)
+__attribute__((unused)) static inline void command_p1(int cmd)
 {
     sdram_dfii_pi1_command_write(cmd);
     sdram_dfii_pi1_command_issue_write(1);
 }
-__attribute__((unused)) static void command_p2(int cmd)
+__attribute__((unused)) static inline void command_p2(int cmd)
 {
     sdram_dfii_pi2_command_write(cmd);
     sdram_dfii_pi2_command_issue_write(1);
 }
-__attribute__((unused)) static void command_p3(int cmd)
+__attribute__((unused)) static inline void command_p3(int cmd)
 {
     sdram_dfii_pi3_command_write(cmd);
     sdram_dfii_pi3_command_issue_write(1);
@@ -57,25 +57,31 @@ __attribute__((unused)) static void command_p3(int cmd)
 
 #define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
 
-const unsigned long sdram_dfii_pix_wrdata_addr[SDRAM_PHY_PHASES] = {
-	CSR_SDRAM_DFII_PI0_WRDATA_ADDR,
-	CSR_SDRAM_DFII_PI1_WRDATA_ADDR,
-	CSR_SDRAM_DFII_PI2_WRDATA_ADDR,
-	CSR_SDRAM_DFII_PI3_WRDATA_ADDR
-};
-
-const unsigned long sdram_dfii_pix_rddata_addr[SDRAM_PHY_PHASES] = {
-	CSR_SDRAM_DFII_PI0_RDDATA_ADDR,
-	CSR_SDRAM_DFII_PI1_RDDATA_ADDR,
-	CSR_SDRAM_DFII_PI2_RDDATA_ADDR,
-	CSR_SDRAM_DFII_PI3_RDDATA_ADDR
-};
-
+static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase){
+    switch (phase) {
+        case 0: return CSR_SDRAM_DFII_PI0_WRDATA_ADDR;
+		case 1: return CSR_SDRAM_DFII_PI1_WRDATA_ADDR;
+		case 2: return CSR_SDRAM_DFII_PI2_WRDATA_ADDR;
+		case 3: return CSR_SDRAM_DFII_PI3_WRDATA_ADDR;
+        default: return 0;
+        }
+}
+    
+static inline unsigned long sdram_dfii_pix_rddata_addr(int phase){
+    switch (phase) {
+        case 0: return CSR_SDRAM_DFII_PI0_RDDATA_ADDR;
+		case 1: return CSR_SDRAM_DFII_PI1_RDDATA_ADDR;
+		case 2: return CSR_SDRAM_DFII_PI2_RDDATA_ADDR;
+		case 3: return CSR_SDRAM_DFII_PI3_RDDATA_ADDR;
+        default: return 0;
+        }
+}
+    
 #define DDRX_MR_WRLVL_ADDRESS 1
 #define DDRX_MR_WRLVL_RESET 6
 #define DDRX_MR_WRLVL_BIT 7
 
-static void init_sequence(void)
+static inline void init_sequence(void)
 {
 	/* Release reset */
 	sdram_dfii_pi0_address_write(0x0);
diff --git a/test/reference/ddr4_init.h b/test/reference/ddr4_init.h
index ca4fe21..194ee3c 100644
--- a/test/reference/ddr4_init.h
+++ b/test/reference/ddr4_init.h
@@ -33,22 +33,22 @@
 
 static void cdelay(int i);
 
-__attribute__((unused)) static void command_p0(int cmd)
+__attribute__((unused)) static inline void command_p0(int cmd)
 {
     sdram_dfii_pi0_command_write(cmd);
     sdram_dfii_pi0_command_issue_write(1);
 }
-__attribute__((unused)) static void command_p1(int cmd)
+__attribute__((unused)) static inline void command_p1(int cmd)
 {
     sdram_dfii_pi1_command_write(cmd);
     sdram_dfii_pi1_command_issue_write(1);
 }
-__attribute__((unused)) static void command_p2(int cmd)
+__attribute__((unused)) static inline void command_p2(int cmd)
 {
     sdram_dfii_pi2_command_write(cmd);
     sdram_dfii_pi2_command_issue_write(1);
 }
-__attribute__((unused)) static void command_p3(int cmd)
+__attribute__((unused)) static inline void command_p3(int cmd)
 {
     sdram_dfii_pi3_command_write(cmd);
     sdram_dfii_pi3_command_issue_write(1);
@@ -56,25 +56,31 @@ __attribute__((unused)) static void command_p3(int cmd)
 
 #define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
 
-const unsigned long sdram_dfii_pix_wrdata_addr[SDRAM_PHY_PHASES] = {
-	CSR_SDRAM_DFII_PI0_WRDATA_ADDR,
-	CSR_SDRAM_DFII_PI1_WRDATA_ADDR,
-	CSR_SDRAM_DFII_PI2_WRDATA_ADDR,
-	CSR_SDRAM_DFII_PI3_WRDATA_ADDR
-};
-
-const unsigned long sdram_dfii_pix_rddata_addr[SDRAM_PHY_PHASES] = {
-	CSR_SDRAM_DFII_PI0_RDDATA_ADDR,
-	CSR_SDRAM_DFII_PI1_RDDATA_ADDR,
-	CSR_SDRAM_DFII_PI2_RDDATA_ADDR,
-	CSR_SDRAM_DFII_PI3_RDDATA_ADDR
-};
-
+static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase){
+    switch (phase) {
+        case 0: return CSR_SDRAM_DFII_PI0_WRDATA_ADDR;
+		case 1: return CSR_SDRAM_DFII_PI1_WRDATA_ADDR;
+		case 2: return CSR_SDRAM_DFII_PI2_WRDATA_ADDR;
+		case 3: return CSR_SDRAM_DFII_PI3_WRDATA_ADDR;
+        default: return 0;
+        }
+}
+    
+static inline unsigned long sdram_dfii_pix_rddata_addr(int phase){
+    switch (phase) {
+        case 0: return CSR_SDRAM_DFII_PI0_RDDATA_ADDR;
+		case 1: return CSR_SDRAM_DFII_PI1_RDDATA_ADDR;
+		case 2: return CSR_SDRAM_DFII_PI2_RDDATA_ADDR;
+		case 3: return CSR_SDRAM_DFII_PI3_RDDATA_ADDR;
+        default: return 0;
+        }
+}
+    
 #define DDRX_MR_WRLVL_ADDRESS 1
 #define DDRX_MR_WRLVL_RESET 769
 #define DDRX_MR_WRLVL_BIT 7
 
-static void init_sequence(void)
+static inline void init_sequence(void)
 {
 	/* Release reset */
 	sdram_dfii_pi0_address_write(0x0);
diff --git a/test/reference/sdr_init.h b/test/reference/sdr_init.h
index ced1036..a48d095 100644
--- a/test/reference/sdr_init.h
+++ b/test/reference/sdr_init.h
@@ -27,7 +27,7 @@
 
 static void cdelay(int i);
 
-__attribute__((unused)) static void command_p0(int cmd)
+__attribute__((unused)) static inline void command_p0(int cmd)
 {
     sdram_dfii_pi0_command_write(cmd);
     sdram_dfii_pi0_command_issue_write(1);
@@ -35,15 +35,21 @@ __attribute__((unused)) static void command_p0(int cmd)
 
 #define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
 
-const unsigned long sdram_dfii_pix_wrdata_addr[SDRAM_PHY_PHASES] = {
-	CSR_SDRAM_DFII_PI0_WRDATA_ADDR
-};
-
-const unsigned long sdram_dfii_pix_rddata_addr[SDRAM_PHY_PHASES] = {
-	CSR_SDRAM_DFII_PI0_RDDATA_ADDR
-};
-
-static void init_sequence(void)
+static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase){
+    switch (phase) {
+        case 0: return CSR_SDRAM_DFII_PI0_WRDATA_ADDR;
+        default: return 0;
+        }
+}
+    
+static inline unsigned long sdram_dfii_pix_rddata_addr(int phase){
+    switch (phase) {
+        case 0: return CSR_SDRAM_DFII_PI0_RDDATA_ADDR;
+        default: return 0;
+        }
+}
+    
+static inline void init_sequence(void)
 {
 	/* Bring CKE high */
 	sdram_dfii_pi0_address_write(0x0);