From ba9134a9a82379a7b244a09f08b7260beac05ca0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 20 Jan 2020 19:15:43 +0100 Subject: [PATCH] litedram_gen: set min_l2_data_width to 0 (l2_data_width will use controller's data_width) --- litedram/gen.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/litedram/gen.py b/litedram/gen.py index 9a782cc..c59260f 100644 --- a/litedram/gen.py +++ b/litedram/gen.py @@ -274,14 +274,14 @@ class LiteDRAMCore(SoCSDRAM): kwargs["integrated_rom_size"] = 0 kwargs["integrated_sram_size"] = 0 kwargs["l2_size"] = 0 - kwargs["l2_data_width"] = 32 + kwargs["min_l2_data_width"] = 0 kwargs["with_uart"] = False kwargs["with_timer"] = False kwargs["with_ctrl"] = False kwargs["with_wishbone"] = (cpu_type != None) else: - kwargs["l2_size"] = 0 - kwargs["l2_data_width"] = 32 + kwargs["l2_size"] = 0 + kwargs["min_l2_data_width"] = 0 # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, sys_clk_freq,