diff --git a/test/benchmark.py b/test/benchmark.py index 07463ed..61c55fa 100755 --- a/test/benchmark.py +++ b/test/benchmark.py @@ -39,6 +39,9 @@ class LiteDRAMBenchmarkSoC(SimSoC): **kwargs ) + # make sure that we perform at least one access + bist_length = max(bist_length, self.sdram.controller.interface.data_width // 8) + # BIST Generator --------------------------------------------------------------------------- bist_generator = _LiteDRAMBISTGenerator(self.sdram.crossbar.get_port()) self.submodules.bist_generator = bist_generator diff --git a/test/benchmarks.yml b/test/benchmarks.yml index 8d9b43b..5d926a1 100644 --- a/test/benchmarks.yml +++ b/test/benchmarks.yml @@ -47,4 +47,30 @@ "bist_length": 1024, "bist_random": False, }, + + # latency + "test_8": { + "sdram_module": 'MT48LC16M16', + "sdram_data_width": 32, + "bist_length": 1, + "bist_random": False, + }, + "test_9": { + "sdram_module": 'MT46V32M16', + "sdram_data_width": 32, + "bist_length": 1, + "bist_random": False, + }, + "test_10": { + "sdram_module": 'MT47H64M16', + "sdram_data_width": 32, + "bist_length": 1, + "bist_random": False, + }, + "test_11": { + "sdram_module": 'MT41K128M16', + "sdram_data_width": 16, + "bist_length": 1, + "bist_random": False, + }, } diff --git a/test/run_benchmarks.py b/test/run_benchmarks.py index 3d5178c..ed884ce 100755 --- a/test/run_benchmarks.py +++ b/test/run_benchmarks.py @@ -98,6 +98,14 @@ class BenchmarkResult: def read_efficiency(self): return self.cmd_count() / self.checker_ticks + def write_latency(self): + assert self.config.bist_length == 1, 'Not a latency benchmark' + return self.generator_ticks + + def read_latency(self): + assert self.config.bist_length == 1, 'Not a latency benchmark' + return self.checker_ticks + def parse_output(self, output): bist_pattern = r'{stage}\s+{var}:\s+{value}' @@ -143,6 +151,8 @@ class ResultsSummary: 'read_bandwidth': Fmt('Read bandwidth', 'bps', lambda value: human_readable(value)), 'write_efficiency': Fmt('Write efficiency', '', lambda value: (100, '%')), 'read_efficiency': Fmt('Read efficiency', '', lambda value: (100, '%')), + 'write_latency': Fmt('Write latency', 'clk', lambda value: (1, '')), + 'read_latency': Fmt('Read latency', 'clk', lambda value: (1, '')), } def __init__(self, results): @@ -151,6 +161,10 @@ class ResultsSummary: def by_metric(self, metric): """Returns pairs of value of the given metric and the configuration used for benchmark""" for result in self.results: + # omit the results that should not be used to calculate given metric + if result.config.bist_length == 1 and metric not in ['read_latency', 'write_latency'] \ + or result.config.bist_length != 1 and metric in ['read_latency', 'write_latency']: + continue value = getattr(result, metric)() yield value, result.config @@ -163,7 +177,8 @@ class ResultsSummary: for metric, (_, unit, formatter) in self.metric_formats.items(): for value, config in self.by_metric(metric): mult, prefix = formatter(value) - result = '{:5.1f} {}{}'.format(value * mult, prefix, unit) + value_fmt = '{:5.1f} {}{}' if isinstance(value * mult, float) else '{:5d} {}{}' + result = value_fmt.format(value * mult, prefix, unit) line = fmt.format(module=config.sdram_module, dwidth=config.sdram_data_width, length=config.bist_length, @@ -201,7 +216,7 @@ class ResultsSummary: import matplotlib.pyplot as plt import numpy as np - from matplotlib.ticker import FuncFormatter, PercentFormatter + from matplotlib.ticker import FuncFormatter, PercentFormatter, ScalarFormatter plt.style.use(theme) @@ -214,6 +229,8 @@ class ResultsSummary: 'read_bandwidth': FuncFormatter(bandwidth_formatter_func), 'write_efficiency': PercentFormatter(1.0), 'read_efficiency': PercentFormatter(1.0), + 'write_latency': ScalarFormatter(), + 'read_latency': ScalarFormatter(), } def config_tick_name(config):