From bb214ce8959a86534311c937d9a6820252ac89f5 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 4 May 2016 01:13:00 +0200 Subject: [PATCH] README: remove wip banner and add Features --- README | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/README b/README index c4cb4d7..5c05180 100644 --- a/README +++ b/README @@ -7,9 +7,6 @@ A small footprint and configurable DRAM core - ******************** - * WORK IN PROGRESS * - ******************** [> Intro --------- @@ -35,11 +32,26 @@ by generating the verilog rtl that you will use as a standard core. [> Features ----------- -XXX +PHY: + - Generic SDRAM PHY (vendor agnostic, tested on Xilinx, Altera, Lattice) + - Spartan6 DDR/LPDDR/DDR2/DDR3 PHY (1:2 or 1:4 frequency ratio) + - Kintex7 DDR3 PHY (1:4 frequency ratio) + - Artix7 DDR3 PHY (1:4 frequency ratio) +Core: + - Fully pipelined, high performance. + - Configurable commands depth on bankmachines. +Frontend: + - Configurable crossbar (simply declare your crossbar and use crossbar.get_port() to add a new port!) + - Ports arbitration transparent to the user. + - Wishbone bridge. + - DMA reader/writer. + - BIST. [> Possible improvements ------------------------- -- +- add standardized interfaces (AXI, Avalon-ST) +- add support for Altera PHYs. +- add support for Lattice PHYs. - ... See below Support and consulting :) If you want to support these features, please contact us at florent [AT]