From bba491396f69848078a47d9f05ff43e1e99818a0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 15 Aug 2018 17:03:06 +0200 Subject: [PATCH] core/bankmachine: fix auto_precharge (OR on the two buffers for req.lock), don't need to wait for precharge timer to issue auto-precharge --- litedram/core/bankmachine.py | 29 +++++++++-------------------- 1 file changed, 9 insertions(+), 20 deletions(-) diff --git a/litedram/core/bankmachine.py b/litedram/core/bankmachine.py index 5d68737..1efa0e5 100644 --- a/litedram/core/bankmachine.py +++ b/litedram/core/bankmachine.py @@ -43,27 +43,16 @@ class BankMachine(Module): # Command buffer cmd_buffer_layout = [("we", 1), ("adr", len(req.adr))] - if settings.with_auto_precharge: - cmd_buffer_lookahead = stream.SyncFIFO(cmd_buffer_layout, settings.cmd_buffer_depth) - cmd_buffer = stream.Buffer(cmd_buffer_layout) # 1 depth buffer to detect row change - self.submodules += cmd_buffer_lookahead, cmd_buffer - self.comb += [ - req.connect(cmd_buffer_lookahead.sink, omit=["wdata_valid", "wdata_ready", - "rdata_valid", "rdata_ready", - "lock"]), - cmd_buffer_lookahead.source.connect(cmd_buffer.sink) - ] - else: - cmd_buffer = stream.SyncFIFO(cmd_buffer_layout, settings.cmd_buffer_depth) - self.submodules += cmd_buffer - self.comb += [ - req.connect(cmd_buffer.sink, omit=["wdata_valid", "wdata_ready", - "rdata_valid", "rdata_ready", - "lock"]) - ] + cmd_buffer_lookahead = stream.SyncFIFO(cmd_buffer_layout, settings.cmd_buffer_depth) + cmd_buffer = stream.Buffer(cmd_buffer_layout) # 1 depth buffer to detect row change + self.submodules += cmd_buffer_lookahead, cmd_buffer self.comb += [ + req.connect(cmd_buffer_lookahead.sink, omit=["wdata_valid", "wdata_ready", + "rdata_valid", "rdata_ready", + "lock"]), + cmd_buffer_lookahead.source.connect(cmd_buffer.sink), cmd_buffer.source.ready.eq(req.wdata_ready | req.rdata_valid), - req.lock.eq(cmd_buffer.source.valid), + req.lock.eq(cmd_buffer_lookahead.source.valid | cmd_buffer.source.valid), ] slicer = _AddressSlicer(settings.geom.colbits, address_align) @@ -106,7 +95,7 @@ class BankMachine(Module): self.comb += [ If(cmd_buffer_lookahead.source.valid & cmd_buffer.source.valid, If(slicer.row(cmd_buffer_lookahead.source.adr) != slicer.row(cmd_buffer.source.adr), - auto_precharge.eq(self.precharge_timer.done & (track_close == 0)) + auto_precharge.eq((track_close == 0)) ) ) ]