From bc8a9cef7de4a56504f30eddce3963b2aa518fe0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 29 Aug 2018 16:34:53 +0200 Subject: [PATCH] README: update --- README | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/README b/README index f7718ed..23c1663 100644 --- a/README +++ b/README @@ -37,10 +37,11 @@ PHY: Core: - Fully pipelined, high performance. - Configurable commands depth on bankmachines. + - Auto-Precharge. Frontend: - Configurable crossbar (simply declare your crossbar and use crossbar.get_port() to add a new port!) - Ports arbitration transparent to the user. - - Wishbone bridge. + - Native, AXI-MM or Wishbone user interface. - DMA reader/writer. - BIST. @@ -52,7 +53,7 @@ LiteDRAM is already used in commercial and open-source designs: [> Possible improvements ------------------------ -- add standardized interfaces (AXI, Avalon-ST) +- add Avalon-ST interface. - add support for Altera PHYs. - add support for Lattice PHYs. - add more documentation