From bd402689615ad502a02143399b65683b22153260 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 28 Oct 2016 09:48:25 +0200 Subject: [PATCH] frontend/dma: add fifo_buffered parameter --- litedram/frontend/dma.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/litedram/frontend/dma.py b/litedram/frontend/dma.py index 9008b11..13e1b7e 100644 --- a/litedram/frontend/dma.py +++ b/litedram/frontend/dma.py @@ -4,7 +4,7 @@ from litex.soc.interconnect import stream class LiteDRAMDMAReader(Module): - def __init__(self, port, fifo_depth=16): + def __init__(self, port, fifo_depth=16, fifo_buffered=False): self.sink = sink = stream.Endpoint([("address", port.aw)]) self.source = source = stream.Endpoint([("data", port.dw)]) @@ -37,7 +37,7 @@ class LiteDRAMDMAReader(Module): self.comb += request_enable.eq(rsv_level != fifo_depth) # FIFO - fifo = stream.SyncFIFO([("data", port.dw)], fifo_depth) + fifo = stream.SyncFIFO([("data", port.dw)], fifo_depth, fifo_buffered) self.submodules += fifo self.comb += [ @@ -48,13 +48,13 @@ class LiteDRAMDMAReader(Module): class LiteDRAMDMAWriter(Module): - def __init__(self, port, fifo_depth=16): + def __init__(self, port, fifo_depth=16, fifo_buffered=False): self.sink = sink = stream.Endpoint([("address", port.aw), ("data", port.dw)]) # # # - fifo = stream.SyncFIFO([("data", port.dw)], fifo_depth) + fifo = stream.SyncFIFO([("data", port.dw)], fifo_depth, fifo_buffered) self.submodules += fifo self.comb += [