From bf9b3609d9904fb73664038bf88f0879a41b013c Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 1 Nov 2021 21:46:39 +0100
Subject: [PATCH] frontend/fifo/LiteDRAMFIFO: Describe parameters.

---
 litedram/frontend/fifo.py | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/litedram/frontend/fifo.py b/litedram/frontend/fifo.py
index 35d4f9b..8620ddd 100644
--- a/litedram/frontend/fifo.py
+++ b/litedram/frontend/fifo.py
@@ -205,6 +205,21 @@ class LiteDRAMFIFO(Module):
 
         Once we no longer have data in the Pre-Converter/DRAM FIFO/Post-Converter path and Pre-FIFO's
         level is below threshold, the modules switches back to Bypass mode.
+
+    Parameters
+    ----------
+    data_width : int, in
+        FIFO data-width.
+    base : int, in
+        FIFO base address in DRAM (bytes).
+    depth: in, in
+        FIFO depth (bytes).
+    write_port: LiteDRAMNativePort
+        DRAM Write port.
+    read_port: LiteDRAMNativePort
+        DRAM Read port.
+    with_bypass: bool, in
+        Automatic Bypass Mode Enable.
     """
     def __init__(self, data_width, base, depth, write_port, read_port, with_bypass=False,
         pre_fifo_depth  = 16,